Displaying 8 results from an estimated 8 matches for "lbb0_6".
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lbb0_1
2010 Oct 07
2
[LLVMdev] [Q] x86 peephole deficiency
...ficiency of the x86
peephole optimizer (or jump-threader?). Here is what I get:
andl $3, %edi
je .LBB0_4
# BB#2: # %nz
# in Loop: Header=BB0_1
Depth=1
cmpl $2, %edi
je .LBB0_6
# BB#3: # %nz.non-middle
# in Loop: Header=BB0_1
Depth=1
cmpl $2, %edi
jbe .LBB0_4
# BB#5: # %sw.bb6
ret
the second 'cmpl' is totally redundant, wh...
2014 Jul 23
4
[LLVMdev] the clang 3.5 loop optimizer seems to jump in unintentional for simple loops
...movdqa %xmm0, %xmm1
movhlps %xmm1, %xmm1 # xmm1 = xmm1[1,1]
paddd %xmm0, %xmm1
pshufd $1, %xmm1, %xmm0 # xmm0 = xmm1[1,0,0,0]
paddd %xmm1, %xmm0
movd %xmm0, %eax
cmpq %rdx, %rsi
je .LBB0_7
.align 16, 0x90
.LBB0_6: # %scalar.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi), %eax
addq $4, %rdi
cmpq %rcx, %rdi
jb .LBB0_6
.LBB0_7: # %._crit_edge
retq
isn't t...
2010 Oct 07
0
[LLVMdev] [Q] x86 peephole deficiency
...or jump-threader?). Here is what I get:
>
>
> andl $3, %edi
> je .LBB0_4
> # BB#2: # %nz
> # in Loop: Header=BB0_1
> Depth=1
> cmpl $2, %edi
> je .LBB0_6
> # BB#3: # %nz.non-middle
> # in Loop: Header=BB0_1
> Depth=1
> cmpl $2, %edi
> jbe .LBB0_4
> # BB#5: # %sw.bb6
> ret
>
> the secon...
2013 Aug 19
3
[LLVMdev] Issue with X86FrameLowering __chkstk on Windows 8 64-bit / Visual Studio 2012
...], 1
.LBB0_3: # %merged
test byte ptr [rbp - 1], -128
je .LBB0_4
# BB#5: # %else4
mov eax, 16
call __chkstk
sub rsp, rax
mov byte ptr [rcx + 148], 1
jmp .LBB0_6
.LBB0_4: # %then3
mov eax, 16
call __chkstk
sub rsp, rax
mov byte ptr [rcx + 148], 0
.LBB0_6: # %merged2
mov eax, dword ptr [rbp - 4]
mov dword ptr [rcx], eax...
2013 Aug 27
0
[LLVMdev] Issue with X86FrameLowering __chkstk on Windows 8 64-bit / Visual Studio 2012
...# %merged
> test byte ptr [rbp - 1], -128
> je .LBB0_4
> # BB#5: # %else4
> mov eax, 16
> call __chkstk
> sub rsp, rax
> mov byte ptr [rcx + 148], 1
> jmp .LBB0_6
> .LBB0_4: # %then3
> mov eax, 16
> call __chkstk
> sub rsp, rax
> mov byte ptr [rcx + 148], 0
> .LBB0_6: # %merged2
> mov eax, dword ptr [rbp - 4]
>...
2011 Oct 19
0
[LLVMdev] Question regarding basic-block placement optimization
...movq %rsi, %r14
movl %edi, %ebp
cmpl $2, 4(%r14)
jb .LBB0_2
.LBB0_2: # %else1
cmpl $3, 8(%r14)
jb .LBB0_4
.LBB0_4: # %else2
cmpl $4, 12(%r14)
jb .LBB0_6
.LBB0_6: # %else3
cmpl $5, 16(%r14)
jb .LBB0_8
.LBB0_8: # %else4
cmpl $4, 12(%r14)
jb .LBB0_10
.LBB0_10: # %exit
movl %ebx, %eax
popq %rb...
2010 Oct 13
2
[LLVMdev] [Q] x86 peephole deficiency
...I get:
>>
>>
>> andl $3, %edi
>> je .LBB0_4
>> # BB#2: # %nz
>> # in Loop: Header=BB0_1
>> Depth=1
>> cmpl $2, %edi
>> je .LBB0_6
>> # BB#3: # %nz.non-middle
>> # in Loop: Header=BB0_1
>> Depth=1
>> cmpl $2, %edi
>> jbe .LBB0_4
>> # BB#5: # %sw.bb6
>>...
2011 Oct 19
3
[LLVMdev] Question regarding basic-block placement optimization
On Tue, Oct 18, 2011 at 6:58 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:
>
> On Oct 18, 2011, at 5:22 PM, Chandler Carruth wrote:
>
> As for why it should be an IR pass, mostly because once the selection dag
>> runs through the code, we can never recover all of the freedom we have at
>> the IR level. To start with, splicing MBBs around requires known about