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...(var(v[data$yr==Y])^.5) + upper _ mean(v[data$yr==Y])+(var(v[data$yr==Y])^.5) + ML _ mlv[ML$yr==Y & ML$metcode==met] + diff _ 0 + if (ML<lower) {diff <- lower-ML; v <<- v-diff} + } > Same line works fine?? Some fuctions in the same script work fine....ie. >adj _ function(x,F,lastf) { + if (F>0) {x[x>F & x < lastf] <<- x[x>F & x < lastf]*.95} + if (F<0) {x[x<F & x > lastf] <<- x[x<F & x > lastf]*.95} + } > The script has never been opened in a windows machine and I would swear that it worked last week. Any ideas?...

Howdy, Running a FPGA design tool (Actel's Designer), I find that it works pretty good, but that certain printed status strings are being formatted incorrectly. It does not seem to affect the operation of the application, except for the status reports. For example, running wine --debugmsg +text,+string,+win /d/Actel/bin/designer and opening an existing design gives this: