Displaying 20 results from an estimated 27 matches for "last_level".
2018 Dec 19
0
[PATCH 07/10] drm/virtio: params struct for virtio_gpu_cmd_create_resource_3d()
...00644
--- a/drivers/gpu/drm/virtio/virtgpu_drv.h
+++ b/drivers/gpu/drm/virtio/virtgpu_drv.h
@@ -59,6 +59,14 @@ struct virtio_gpu_object_params {
uint32_t height;
unsigned long size;
bool pinned;
+ /* 3d */
+ uint32_t target;
+ uint32_t bind;
+ uint32_t depth;
+ uint32_t array_size;
+ uint32_t last_level;
+ uint32_t nr_samples;
+ uint32_t flags;
};
struct virtio_gpu_object {
@@ -313,7 +321,7 @@ void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
void
virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
struct virtio_gpu_object *bo,
- struct virti...
2019 Mar 18
0
[PATCH v3 4/5] drm/virtio: params struct for virtio_gpu_cmd_create_resource_3d()
...44
--- a/drivers/gpu/drm/virtio/virtgpu_drv.h
+++ b/drivers/gpu/drm/virtio/virtgpu_drv.h
@@ -55,6 +55,14 @@ struct virtio_gpu_object_params {
uint32_t width;
uint32_t height;
unsigned long size;
+ /* 3d */
+ uint32_t target;
+ uint32_t bind;
+ uint32_t depth;
+ uint32_t array_size;
+ uint32_t last_level;
+ uint32_t nr_samples;
+ uint32_t flags;
};
struct virtio_gpu_object {
@@ -309,7 +317,7 @@ void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
void
virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
struct virtio_gpu_object *bo,
- struct virti...
2010 Jan 18
0
[PATCH] nv04-nv40: Rewrite and unify miptree and transfer code
...rm pitch must be linear, and vice versa */
+ if(!util_format_is_compressed(pt->format)
+ && (uniform_pitch || mt->base.tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR))
+ {
+ mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
+ uniform_pitch = 1;
+ }
- for (l = 0; l <= pt->last_level; l++) {
- nv04mt->level[l].pitch = pt->width0;
- nv04mt->level[l].pitch = (nv04mt->level[l].pitch + 63) & ~63;
+ if(uniform_pitch)
+ {
+ mt->linear_pitch = util_format_get_stride(pt->format, pt->width0);
+
+ // TODO: this is only a constraint for rendering and not sampl...
2010 Jan 18
0
[PATCH] nv04-nv40: Rewrite and unify miptree and transfer code (v2)
...rm pitch must be linear, and vice versa */
+ if(!util_format_is_compressed(pt->format)
+ && (uniform_pitch || mt->base.tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR))
+ {
+ mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR;
+ uniform_pitch = 1;
+ }
- for (l = 0; l <= pt->last_level; l++) {
- nv04mt->level[l].pitch = pt->width0;
- nv04mt->level[l].pitch = (nv04mt->level[l].pitch + 63) & ~63;
+ if(uniform_pitch)
+ {
+ mt->linear_pitch = util_format_get_stride(pt->format, pt->width0);
+
+ // TODO: this is only a constraint for rendering and not sampl...
2014 May 18
0
[PATCH] nv50,nvc0: fix 3d blits with mipmap levels
...y);
y1 *= (float)(1 << nv50_miptree(src)->ms_y);
+ /* XXX: multiply by 6 for cube arrays ? */
+ dz = (float)info->src.box.depth / (float)info->dst.box.depth;
+ z = (float)info->src.box.z;
+ if (nv50_miptree(src)->layout_3d)
+ z += 0.5f * dz;
+
if (src->last_level > 0) {
/* If there are mip maps, GPU always assumes normalized coordinates. */
const unsigned l = info->src.level;
@@ -1151,14 +1157,12 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
x1 /= fh;
y0 /= fv;
y1 /= fv;
+ if (nv5...
2016 Feb 15
2
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...width = mt->base.base.width0;
> + height = mt->base.base.height0;
> + }
> +
> + tic[4] |= width - 1;
> +
> + tic[5] |= (height - 1) & 0xffff;
> + tic[5] |= (depth - 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
> + tic[3] |= mt->base.base.last_level << GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT;
> +
> + /* sampling points: (?) */
> + if ((flags & NV50_TEXVIEW_ACCESS_RESOLVE) && mt->ms_x > 1) {
> + tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO;
> + tic[6] |= GM107_TIC2_6_MAX_ANISOTROPY_2...
2009 Dec 26
2
[MESA PATCH] Fix nv40_miptree_layout pitch
...rc/gallium/drivers/nv40/nv40_miptree.c
b/src/gallium/drivers/nv40/nv40_miptree.c
index b974e68..9f54187 100644
--- a/src/gallium/drivers/nv40/nv40_miptree.c
+++ b/src/gallium/drivers/nv40/nv40_miptree.c
@@ -31,8 +31,8 @@ nv40_miptree_layout(struct nv40_miptree *mt)
}
for (l = 0; l <= pt->last_level; l++) {
- if (wide_pitch && (pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR))
- mt->level[l].pitch = align(util_format_get_stride(pt->format,
pt->width0), 64);
+ if (wide_pitch)
+ mt->level[l].pitch = align(util_format_get_stride(pt->format, width), 64);
else...
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...ht0 << mt->ms_y;
+ } else {
+ width = mt->base.base.width0;
+ height = mt->base.base.height0;
+ }
+
+ tic[4] |= width - 1;
+
+ tic[5] |= (height - 1) & 0xffff;
+ tic[5] |= (depth - 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
+ tic[3] |= mt->base.base.last_level << GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT;
+
+ /* sampling points: (?) */
+ if ((flags & NV50_TEXVIEW_ACCESS_RESOLVE) && mt->ms_x > 1) {
+ tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO;
+ tic[6] |= GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1;
+ } else {
+...
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...idth0;
>> + height = mt->base.base.height0;
>> + }
>> +
>> + tic[4] |= width - 1;
>> +
>> + tic[5] |= (height - 1) & 0xffff;
>> + tic[5] |= (depth - 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
>> + tic[3] |= mt->base.base.last_level << GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT;
>> +
>> + /* sampling points: (?) */
>> + if ((flags & NV50_TEXVIEW_ACCESS_RESOLVE) && mt->ms_x > 1) {
>> + tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO;
>> + tic[6] |= GM107_TIC...
2015 Sep 21
2
[PATCH v2 4/6] virtio-gpu: add 3d/virgl support
...lidate_buffer mainbuf;
+ struct virtio_gpu_fence *fence = NULL;
+ struct ww_acquire_ctx ticket;
+ struct virtio_gpu_resource_create_3d rc_3d;
+
+ if (vgdev->has_virgl_3d == false) {
+ if (rc->depth > 1)
+ return -EINVAL;
+ if (rc->nr_samples > 1)
+ return -EINVAL;
+ if (rc->last_level > 1)
+ return -EINVAL;
+ if (rc->target != 2)
+ return -EINVAL;
+ if (rc->array_size > 1)
+ return -EINVAL;
+ }
+
+ INIT_LIST_HEAD(&validate_list);
+ memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
+
+ virtio_gpu_resource_id_get(vgdev, &res_id);
+
+ size = r...
2015 Sep 21
2
[PATCH v2 4/6] virtio-gpu: add 3d/virgl support
...lidate_buffer mainbuf;
+ struct virtio_gpu_fence *fence = NULL;
+ struct ww_acquire_ctx ticket;
+ struct virtio_gpu_resource_create_3d rc_3d;
+
+ if (vgdev->has_virgl_3d == false) {
+ if (rc->depth > 1)
+ return -EINVAL;
+ if (rc->nr_samples > 1)
+ return -EINVAL;
+ if (rc->last_level > 1)
+ return -EINVAL;
+ if (rc->target != 2)
+ return -EINVAL;
+ if (rc->array_size > 1)
+ return -EINVAL;
+ }
+
+ INIT_LIST_HEAD(&validate_list);
+ memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
+
+ virtio_gpu_resource_id_get(vgdev, &res_id);
+
+ size = r...
2015 Oct 02
0
[PATCH v3 4/7] virtio-gpu: add 3d/virgl support
...lidate_buffer mainbuf;
+ struct virtio_gpu_fence *fence = NULL;
+ struct ww_acquire_ctx ticket;
+ struct virtio_gpu_resource_create_3d rc_3d;
+
+ if (vgdev->has_virgl_3d == false) {
+ if (rc->depth > 1)
+ return -EINVAL;
+ if (rc->nr_samples > 1)
+ return -EINVAL;
+ if (rc->last_level > 1)
+ return -EINVAL;
+ if (rc->target != 2)
+ return -EINVAL;
+ if (rc->array_size > 1)
+ return -EINVAL;
+ }
+
+ INIT_LIST_HEAD(&validate_list);
+ memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
+
+ virtio_gpu_resource_id_get(vgdev, &res_id);
+
+ size = r...
2015 Oct 02
0
[PATCH v3 4/7] virtio-gpu: add 3d/virgl support
...lidate_buffer mainbuf;
+ struct virtio_gpu_fence *fence = NULL;
+ struct ww_acquire_ctx ticket;
+ struct virtio_gpu_resource_create_3d rc_3d;
+
+ if (vgdev->has_virgl_3d == false) {
+ if (rc->depth > 1)
+ return -EINVAL;
+ if (rc->nr_samples > 1)
+ return -EINVAL;
+ if (rc->last_level > 1)
+ return -EINVAL;
+ if (rc->target != 2)
+ return -EINVAL;
+ if (rc->array_size > 1)
+ return -EINVAL;
+ }
+
+ INIT_LIST_HEAD(&validate_list);
+ memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
+
+ virtio_gpu_resource_id_get(vgdev, &res_id);
+
+ size = r...
2015 Sep 21
0
[PATCH v2 4/6] virtio-gpu: add 3d/virgl support
...nce *fence = NULL;
> + struct ww_acquire_ctx ticket;
> + struct virtio_gpu_resource_create_3d rc_3d;
> +
> + if (vgdev->has_virgl_3d == false) {
> + if (rc->depth > 1)
> + return -EINVAL;
> + if (rc->nr_samples > 1)
> + return -EINVAL;
> + if (rc->last_level > 1)
> + return -EINVAL;
> + if (rc->target != 2)
> + return -EINVAL;
> + if (rc->array_size > 1)
> + return -EINVAL;
> + }
> +
> + INIT_LIST_HEAD(&validate_list);
> + memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
> +
> + virti...
2019 Apr 10
0
[PATCH 3/3] virtio-gpu api: VIRTIO_GPU_F_RESSOURCE_V2
...fset[4];
};
+/* VIRTIO_GPU_CMD_RESOURCE_CREATE_V2 */
+struct virtio_gpu_cmd_resource_create_v2 {
+ struct virtio_gpu_ctrl_hdr hdr;
+ __le32 resource_id;
+ __le32 format;
+ __le32 width;
+ __le32 height;
+ /* 3d only */
+ __le32 target;
+ __le32 bind;
+ __le32 depth;
+ __le32 array_size;
+ __le32 last_level;
+ __le32 nr_samples;
+ __le32 flags;
+};
+
+/* VIRTIO_GPU_RESP_OK_RESOURCE_INFO */
+struct virtio_gpu_resp_resource_info {
+ struct virtio_gpu_ctrl_hdr hdr;
+ __le32 stride[4];
+ __le32 size[4];
+};
+
#define VIRTIO_GPU_CAPSET_VIRGL 1
#define VIRTIO_GPU_CAPSET_VIRGL2 2
--
2.18.1
2019 Apr 11
0
[PATCH 3/3] virtio-gpu api: VIRTIO_GPU_F_RESSOURCE_V2
...esource_id;
> > + __le32 format;
> > + __le32 width;
> > + __le32 height;
> > + /* 3d only */
> > + __le32 target;
> > + __le32 bind;
> > + __le32 depth;
> > + __le32 array_size;
> > + __le32 last_level;
> > + __le32 nr_samples;
> > + __le32 flags;
> > +};
>
>
> I assume this is always backed by some host side allocation, without any
> guest side pages associated with it?
No. It is not backed at all yet. Workflow would be like this:
(1) VIRTIO_GPU_...
2014 Sep 01
0
[PATCH] nvc0: don't make 1d staging textures linear
...lium/drivers/nouveau/nvc0/nvc0_miptree.c
@@ -261,7 +261,6 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
if (pt->usage == PIPE_USAGE_STAGING) {
switch (pt->target) {
- case PIPE_TEXTURE_1D:
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
if (pt->last_level == 0 &&
--
1.8.5.5
2019 Apr 12
2
[PATCH 3/3] virtio-gpu api: VIRTIO_GPU_F_RESSOURCE_V2
...width;
> > > > + __le32 height;
> > > > + /* 3d only */
> > > > + __le32 target;
> > > > + __le32 bind;
> > > > + __le32 depth;
> > > > + __le32 array_size;
> > > > + __le32 last_level;
> > > > + __le32 nr_samples;
> > > > + __le32 flags;
> > > > +};
> > >
> > >
> > > I assume this is always backed by some host side allocation, without any
> > > guest side pages associated with it?
> >
>...
2019 Apr 12
2
[PATCH 3/3] virtio-gpu api: VIRTIO_GPU_F_RESSOURCE_V2
...width;
> > > > + __le32 height;
> > > > + /* 3d only */
> > > > + __le32 target;
> > > > + __le32 bind;
> > > > + __le32 depth;
> > > > + __le32 array_size;
> > > > + __le32 last_level;
> > > > + __le32 nr_samples;
> > > > + __le32 flags;
> > > > +};
> > >
> > >
> > > I assume this is always backed by some host side allocation, without any
> > > guest side pages associated with it?
> >
>...
2015 Sep 09
3
[PATCH 3/5] update virtio gpu driver: add 3d/virgl support
...lidate_buffer mainbuf;
+ struct virtio_gpu_fence *fence = NULL;
+ struct ww_acquire_ctx ticket;
+ struct virtio_gpu_resource_create_3d rc_3d;
+
+ if (vgdev->has_virgl_3d == false) {
+ if (rc->depth > 1)
+ return -EINVAL;
+ if (rc->nr_samples > 1)
+ return -EINVAL;
+ if (rc->last_level > 1)
+ return -EINVAL;
+ if (rc->target != 2)
+ return -EINVAL;
+ if (rc->array_size > 1)
+ return -EINVAL;
+ }
+
+ INIT_LIST_HEAD(&validate_list);
+ memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
+
+ virtio_gpu_resource_id_get(vgdev, &res_id);
+
+ size = r...