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lantech
2018 Apr 05
1
A9 Scheduler
...raries,
latencies defined in the SchedReadWrite representation which are mapped
through SchedAlias to the ANDri and, in the end, a mapping (or overriding?)
of the latencies in the Itineraries by the processor-specific SchedWrites,
through the InstRW?
Can someone share some light on what scheduling/lantecy information is
being used in this case? I cannot get my head around this... What am I
missing here?
Note: I also do not understand why use instregex if we could use the IIC_*
for the InstRW.
Thanks.
- Tiago
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