search for: langintro

...o has “bang operators” which have a wide variety of meanings:' > > I would be very thankful if someone can explain it to me. > > e.g. what does "!strconcat" or "!if" mean? Those are defined in the "Language Introduction": http://llvm.org/docs/TableGen/LangIntro.html#tablegen-values-and-expressions Not sure why we have things split into three separate pages: * TableGen - http://llvm.org/docs/TableGen/index.html * Introduction - http://llvm.org/docs/TableGen/LangIntro.html * Reference - http://llvm.org/docs/TableGen/LangRef.html I consistently fi...

Hello all, I don't find anything helping me understand the llvm bang operator. In the llvm TableGen language reference, it only says: 'TableGen also has “bang operators” which have a wide variety of meanings: *'* I would be very thankful if someone can explain it to me. e.g. what does "!strconcat" or "!if" mean? Cheers ES -------------- next part --------------

Hello, http://llvm.org/docs/TableGen/LangIntro.html says I can use octal integer value (indicated by a leading 0). In fact the number is converted to decimal. With best regards, Romick.

...of > meanings:' > > > > I would be very thankful if someone can explain it to me. > > > > e.g. what does "!strconcat" or "!if" mean? > > Those are defined in the "Language Introduction": > > > http://llvm.org/docs/TableGen/LangIntro.html#tablegen-values-and-expressions > > Not sure why we have things split into three separate pages: > > * TableGen - http://llvm.org/docs/TableGen/index.html > > * Introduction - http://llvm.org/docs/TableGen/LangIntro.html > > * Reference - http://llvm.org/docs/Tabl...

...ly academic paper) describing TableGen's typing of the following fields used to describe Instruction: pattern, ins and outs. I found a few pages on TableGen, but none of them talking about these fields: http://llvm.org/docs/TableGen/LangRef.html http://llvm.org/docs/TableGen/LangIntro.html http://llvm.org/docs/TableGen/index.html http://llvm.org/docs/TableGen/BackEnds.html http://llvm.org/docs/CodeGenerator.html) Although not (really) about TableGen, I found a good paper talking about the instruction selection in LLVM: http://llvm.org/pubs/2008-CGO-Da...

...nd acyclic. >> > > > Am I correct in my understanding that each node can either be a register > or of type SDNode defined in TargetSelectionDAG.td? > I should clarify. What I'm confused about is how exactly the DAG is defined. Here is what is says on llvm.org/docs/TableGen/LangIntro.html (DEF a, b)a dag value. The first element is required to be a record definition, the remaining elements in the list may be arbitrary other values, including nested `dag‘ values.What is meant by a record definition? Is it a definition of type SDNode which are defined in TargetSelectionDAG.td? Wh...

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with its operands being subnodes. > >

Eric Christopher <echristo at gmail.com> writes: > +David Greene<mailto:dag at cray.com> as someone who might have an opinion. > > I don't have a strong opinion, but if someone wants to try to make the > docs better and more friendly to them I'm totally down :) Thanks for the CC. I think combining them makes sense. I recall having similar issues finding things

Hi Krzystof, regarding your first solution (creating separate instruction), is it possible to somehow have cascading defm? for example, let's suppose aaa is a 3-bit condition a, and bb is a 2-bit condition b, all in one instruction, instead of having one multiclass with 2^5 conditions, is it possible to write 2^3 "a" conditions, and 2^2 "b" conditions, and the rest taken

...> >> Am I correct in my understanding that each node can either be a register >> or of type SDNode defined in TargetSelectionDAG.td? >> > > I should clarify. What I'm confused about is how exactly the DAG is > defined. Here is what is says on llvm.org/docs/TableGen/LangIntro.html > (DEF a, b)a dag value. The first element is required to be a record > definition, the remaining elements in the list may be arbitrary other > values, including nested `dag‘ values.What is meant by a record > definition? Is it a definition of type SDNode which are defined in >...

Welcome to all Questions from veteran programmer with no LLVM backend experience evaluating llvm for creating a Hitachi 6309 backend. This post is about finding out more about machine instruction operands. The documentation I have read so far includes: - the online manuals - Building an LLVM Backend. Fraser Cormack Pierre-André Saulais - The Design of a Custom 32-bit RISC CPU