search for: lanaiinstrinfo

Displaying 4 results from an estimated 4 matches for "lanaiinstrinfo".

2016 Nov 23
4
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
Hi All. This is an RFC for a proposed target specific X86 optimization for reducing code size in the encoding of AVX-512 instructions when possible. When the AVX512F instruction set was introduced in X86 it included additional 32 registers of 512bit size each ZMM0 - ZMM31, as well as additional 16 XMM registers XMM16-XMM31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of
2016 Nov 23
2
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
...rget/Mips/MipsDSPInstrFormats.td > lib/Target/Mips/MipsInstrFormats.td > lib/Target/Mips/Mips32r6InstrFormats.td > lib/Target/PowerPC/PPC.td > lib/Target/AMDGPU/SIInstrInfo.td > lib/Target/AMDGPU/R600Instructions.td > lib/Target/SystemZ/SystemZInstrFormats.td > lib/Target/Lanai/LanaiInstrInfo.td > > I've used this feature a few times in the PowerPC backend, and it's quite > convenient. > > -Hal > > No need for special Opt flags, as it is always better to use the reduced > VEX encoding when possible. > > > > Thank you for any comments or quest...
2016 Nov 24
3
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
...ib/Target/Hexagon/Hexagon.td lib/Target/Mips/MipsDSPInstrFormats.td lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/Mips32r6InstrFormats.td lib/Target/PowerPC/PPC.td lib/Target/AMDGPU/SIInstrInfo.td lib/Target/AMDGPU/R600Instructions.td lib/Target/SystemZ/SystemZInstrFormats.td lib/Target/Lanai/LanaiInstrInfo.td I've used this feature a few times in the PowerPC backend, and it's quite convenient. -Hal No need for special Opt flags, as it is always better to use the reduced VEX encoding when possible. Thank you for any comments or questions that you may have. Sincerely, Gadi. -----------...
2016 Nov 28
2
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
...ib/Target/Hexagon/Hexagon.td lib/Target/Mips/MipsDSPInstrFormats.td lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/Mips32r6InstrFormats.td lib/Target/PowerPC/PPC.td lib/Target/AMDGPU/SIInstrInfo.td lib/Target/AMDGPU/R600Instructions.td lib/Target/SystemZ/SystemZInstrFormats.td lib/Target/Lanai/LanaiInstrInfo.td I've used this feature a few times in the PowerPC backend, and it's quite convenient. -Hal No need for special Opt flags, as it is always better to use the reduced VEX encoding when possible. Thank you for any comments or questions that you may have. Sincerely, Gadi. ------------...