search for: lamprineas

Displaying 10 results from an estimated 10 matches for "lamprineas".

2018 Aug 10
2
llvm MemorySSA def-use chains
...assume.ll has ; RUN: opt -aa-pipeline=basic-aa -passes='print<memoryssa>,verify<memoryssa>' without basic-aa the memory ssa will safely assume that the stores to %a and %d alias which may be proven disjoint by one of the alias analyses. On Thu, Aug 9, 2018 at 8:37 AM Alexandros Lamprineas via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > > My understanding is that MemorySSA doesn't know whether memory locations can alias or not. > > > Alexandros > > ________________________________ > From: llvm-dev <llvm-dev-bounces at lists.l...
2018 May 04
0
RFC: Are auto-generated assertions a good practice?
On 4 May 2018 at 10:25, Alexandros Lamprineas via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Hello llvm-dev, > > > On a recent code review I was asked to auto-generate assertion checks for my > unit test. I wasn't aware that this was even possible. I am referring to the > python `update` scripts under `utils` di...
2018 May 04
2
RFC: Are auto-generated assertions a good practice?
...s wonder if they're checking full combinatorial expansions that may not be required/desirable - always a tradeoff of just how black/white box tests are. On Fri, May 4, 2018 at 2:56 AM Alex Bradbury via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 4 May 2018 at 10:25, Alexandros Lamprineas via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > Hello llvm-dev, > > > > > > On a recent code review I was asked to auto-generate assertion checks > for my > > unit test. I wasn't aware that this was even possible. I am referring to > the >...
2018 May 04
2
RFC: Are auto-generated assertions a good practice?
Hello llvm-dev, On a recent code review I was asked to auto-generate assertion checks for my unit test. I wasn't aware that this was even possible. I am referring to the python `update` scripts under `utils` directory. My first reaction was wow! I found it very practical and useful. It saves you significant amount of time when writing a regression test. So I gave it a try. The generated
2018 May 04
0
RFC: Are auto-generated assertions a good practice?
...full combinatorial expansions that may > not be required/desirable - always a tradeoff of just how black/white box > tests are. > > On Fri, May 4, 2018 at 2:56 AM Alex Bradbury via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> On 4 May 2018 at 10:25, Alexandros Lamprineas via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >> > Hello llvm-dev, >> > >> > >> > On a recent code review I was asked to auto-generate assertion checks >> for my >> > unit test. I wasn't aware that this was even possible. I am...
2018 May 04
2
RFC: Are auto-generated assertions a good practice?
...ns that may >> not be required/desirable - always a tradeoff of just how black/white box >> tests are. >> >> On Fri, May 4, 2018 at 2:56 AM Alex Bradbury via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >>> On 4 May 2018 at 10:25, Alexandros Lamprineas via llvm-dev >>> <llvm-dev at lists.llvm.org> wrote: >>> > Hello llvm-dev, >>> > >>> > >>> > On a recent code review I was asked to auto-generate assertion checks >>> for my >>> > unit test. I wasn't aware that...
2018 Apr 26
1
[Constant Folder, InstCombine, ARM, AArch64] Question about constant folding of vector load
Hello, There is a particular code sequence I would like to optimize at the IR level. I'd like to turn an Arm/AArch64 table lookup intrinsic that takes a constant vector mask into a shufflevector instruction: vtbl1(V,mask) ~> shufflevector(V,undef,mask) The reason is that if the mask is {7,6,5,4,3,2,1,0}, then the backend will generate rev64 instructions instead. If the mask comes
2018 May 04
0
RFC: Are auto-generated assertions a good practice?
...be required/desirable - always a tradeoff of just how black/white box >>> tests are. >>> >>> On Fri, May 4, 2018 at 2:56 AM Alex Bradbury via llvm-dev < >>> llvm-dev at lists.llvm.org> wrote: >>> >>>> On 4 May 2018 at 10:25, Alexandros Lamprineas via llvm-dev >>>> <llvm-dev at lists.llvm.org> wrote: >>>> > Hello llvm-dev, >>>> > >>>> > >>>> > On a recent code review I was asked to auto-generate assertion checks >>>> for my >>>> > unit te...
2018 May 07
0
LLVM Weekly - #227, May 7th 2018
...to start regular workshop/study-group meetups, and to aim for a 1-day event in October. * Welcome to Mikhail Ramalho who will be working with the Clang static analyzer and Z3 SMT solver [as part of Google Summer of Code](http://lists.llvm.org/pipermail/cfe-dev/2018-May/057831.html). * Alexandros Lamprineas wonders about [best practice for using auto-generated test assertions](http://lists.llvm.org/pipermail/llvm-dev/2018-May/122996.html), such as those generated by `update_llc_test_checks.py`. * Walter Lee has [ported ASan to Myriad RTEMS](http://lists.llvm.org/pipermail/llvm-dev/2018-May/123018.htm...
2018 Aug 09
2
llvm MemorySSA def-use chains
Hi, I have a question about how llvm MemorySSA works, as seems I misunderstand something. Consider following code snippet and corresponding IR with MemorySSA annotations (got with opt -print-memoryssa) void foo(int* b) { int a = 0; int d = 12; if (b) { a = 42; d = 32; } int c = a; int e = d; } ; Function Attrs: noinline nounwind optnone uwtable