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2008 Sep 25
5
[LLVMdev] confused about llvm.memory.barrier
...; <i32> [#uses=1]
12. ret i32 %0
13. }
14.
15. declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
compiled with:
1. llc -mcpu=core2 -mattr=+sse2,+sse3 -f -o test.s test.bc
becomes
1. .text
2. .align 4,0x90
3. .globl __Z3foov
4. __Z3foov:
5. movl L_a$non_lazy_ptr, %eax
6. movl $1, (%eax)
7. nop
8. movl L_b$non_lazy_ptr, %eax
9. movl (%eax), %eax
10. ret
11.
12. .section __IMPORT,__pointers,non_lazy_symbol_pointers
13. L_a$non_lazy_ptr:
14. .indirect_symbol _a
15. .long 0
16. L_b$non_lazy_ptr:
17. .indirect_symbol _b
18. .long 0
19. .sub...
2008 Apr 03
2
[LLVMdev] Alias analysis and instruction level parallelism
Dan Gohman wrote:
> I think this is trickier than it sounds; the reason GEPs are lowered
> is to
> allow strength-reduction and other things to do transformations on them.
> It would require those passes to know how to update the mapping.
Yes, I do appreciate the amount of work involved, and I am
very open to other suggestions.
What the backend really needs to know is what loads