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359
2018 Aug 28
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...ub.com/Lekensteyn/acpi-stuff/blob/master/d3test/XPS9560/slogs/win10-rp-enable-disable.txt#L3418
https://github.com/Lekensteyn/acpi-stuff/blob/master/d3test/XPS9560/slogs/linux-rp.txt
lspci for the emulated bridge:
https://github.com/Lekensteyn/acpi-stuff/blob/master/d3test/XPS9560/lspci-vm-vfio.txt#L359
The rp_*_config trace points are non-standard and require patches:
https://github.com/Lekensteyn/acpi-stuff/blob/master/d3test/patches/qemu-trace.diff
--
Kind regards,
Peter Wu
https://lekensteyn.nl
2018 Aug 28
6
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
On Fri, Aug 24, 2018 at 11:42 PM, Peter Wu <peter at lekensteyn.nl> wrote:
> Are these systems also affected through runtime power management? For
> example:
>
> modprobe nouveau # should enable runtime PM
> sleep 6 # wait for runtime suspend to kick in
> lspci -s1: # runtime resume by reading PCI config space
>
> On laptops from
2017 Dec 15
8
Register Allocation Graph Coloring algorithm and Others
Hi GCC and LLVM developers,
I am learning Register Allocation algorithms and I am clear that:
* Unlimited VirtReg (pseudo) -> limited or fixed or alias[1] PhysReg (hard)
* Memory (20 - 100 cycles) is expensive than Register (1 cycle), but it
has to spill code when PhysReg is unavailable
* Folding spill code into instructions, handling register coallescing,
splitting live ranges, doing