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On Jan 10, 2013, at 9:54 PM, Kenneth Waters <kwwaters at gmail.com> wrote: > I have a pattern where I load the 16 bit portion of the register with 0, and then copy in the 8 bit portion. > > def : Pat<(i16 (zextloadi8 addr:$src)), > (INSERT_SUBREG (MOV16id 0), (MOV8md addr:$src), sub_byte)>; > > which produces wo...

> LLVM's register coalescer and allocator don't try to reschedule > instructions, which seems to be required here. > I think you're right. Looking at the instruction schedules before register allocation, shows that it's scheduling the load before the zero move in one case but not the other. Is there an easy way I can trick the scheduler into putting these in the right

llvm-dev, I'm trying to get a better understanding of sub-registers. I'm seeing the code generator make an odd decision that I was hoping someone could point me in the right direction of explaining. The architecture is 68000, which has 8, 16, and 32 bit views of all of it's data registers. In order to zero extend you can load a big view with zero, and then copy into the small view.

I have a few weeks of downtime between jobs coming up and I was considering trying to put together a m68k backend for LLVM. I have some experience with compiler front ends; I've maintained a couple of DSL implementations in the past, but I have relativly little knowledge of code generation. I know that there have been a few attempts in the past, but I cannot find any evidence that they made