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2009 Jul 06
1
[LLVMdev] Mips -> DLX Modifications as Target
...gram. The main issue I am having is with respect to the following (Note: I have already changed ADDui from ADDiu) We have this def ADDui : ArithI<0x09, "addui", add, simm16, immSExt16>; However sticky speaking this should be in dlx the instructions are addui rk, ri, Kuns (Where Kusn is unsigned) Likewise DLX has a subui rk, ri, Kusn. (Mips does not) Thus they should be: def ADDui : ArithI<0x09, "addui", add, simm16, immZExt16>; def SUBui : ArithI<0x23, "subui", sub, simm16, immZExt16>; However I am not sure how or where to setup in the Ta...