Displaying 6 results from an estimated 6 matches for "krste".
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erste
2016 Nov 27
2
[RFC] Supporting ARM's SVE in LLVM
On 27 November 2016 at 16:51, Amara Emerson <amara.emerson at gmail.com> wrote:
> There is nothing to stop other targets from using
> stepvector/seriesvector. In fact for wide vector targets, often the IR
> constant for representing a step vector is explicitly expressed as
> <i32 0, i32 1, i32 2..> and so on (this gets really cumbersome when
> your vector length is
2016 Nov 28
2
[RFC] Supporting ARM's SVE in LLVM
On 28 November 2016 at 09:15, Alex Bradbury <asb at asbradbury.org> wrote:
> The RISC-V vector proposal is still in the development stage, but it
> will inevitably be vector length agnostic much like Hwacha. Krste gave
> a talk about his proposal for the 'V' extension last year
> <https://riscv.org/wp-content/uploads/2015/06/riscv-vector-workshop-june2015.pdf>
> and I'm looking forward to his update at the RISC-V Workshop this
> Wednesday, not least because I'm hoping he'...
2018 Apr 11
5
RFC: Supporting the RISC-V vector extension in LLVM
...s to a single configuration may be a good first
step to get things up and running, but ultimately support for
runtime-varying vector lengths is desired to make the most of hardware
capabilities.
[4] "A Case for MVPs: Mixed-Precision Vector Processors", Albert Ou, Quan
Nguyen, Yunsup Lee, Krste Asanović,
http://hwacha.org/papers/hwacha-mvp-prism2014.pdf
## Producing vector code
It is intended that vector code is primarily produced via loop
vectorization and other IR-level auto-vectorizers (e.g., the region
vectorizer), not written by hand. Supporting loop vectorization is of
highest pr...
2018 Apr 12
0
RFC: Supporting the RISC-V vector extension in LLVM
...ay be a good first
> step to get things up and running, but ultimately support for
> runtime-varying vector lengths is desired to make the most of hardware
> capabilities.
>
> [4] "A Case for MVPs: Mixed-Precision Vector Processors", Albert Ou, Quan
> Nguyen, Yunsup Lee, Krste Asanović,
> http://hwacha.org/papers/hwacha-mvp-prism2014.pdf
>
>
> ## Producing vector code
>
> It is intended that vector code is primarily produced via loop
> vectorization and other IR-level auto-vectorizers (e.g., the region
> vectorizer), not written by hand. Supportin...
2018 Apr 13
0
RFC: Supporting the RISC-V vector extension in LLVM
...step to get things up and running, but ultimately support for
>> runtime-varying vector lengths is desired to make the most of hardware
>> capabilities.
>>
>> [4] "A Case for MVPs: Mixed-Precision Vector Processors", Albert Ou,
>> Quan Nguyen, Yunsup Lee, Krste Asanović,
>> http://hwacha.org/papers/hwacha-mvp-prism2014.pdf
>>
>>
>> ## Producing vector code
>>
>> It is intended that vector code is primarily produced via loop
>> vectorization and other IR-level auto-vectorizers (e.g., the region
>>...
2018 Apr 16
1
RFC: Supporting the RISC-V vector extension in LLVM
...a single configuration may be a good first step to get things up and running, but ultimately support for runtime-varying vector lengths is desired to make the most of hardware capabilities.
[4] "A Case for MVPs: Mixed-Precision Vector Processors", Albert Ou, Quan Nguyen, Yunsup Lee, Krste Asanović,
http://hwacha.org/papers/hwacha-mvp-prism2014.pdf
## Producing vector code
It is intended that vector code is primarily produced via loop vectorization and other IR-level auto-vectorizers (e.g., the region vectorizer), not written by hand. Supporting loop vectorization is o...