search for: knownzeros

I'm trying to reason about how to find certain bit positions of the absolute value of a given integer value. Specifically, I want to know the highest possibly set bit and lowest possibly set bit of the absolute value, in order to find the range between the two. Note that I'm specifically trying to be as conservative as possible. This is what I have so far: If the sign bit of the

...Phabricator.) +1 In your example, we have: 3 - idx == idx => 3 == 2*idx and you've generalized this slightly to make this: (odd number) == 2*idx which makes sense. I think that we can go further looking at: n == 2*idx and, calling computeKnownBits on n and idx, then asking whether: knownZeros(n) == (knownZeros(idx) << 1) | 1 and knownOnes(n) == knownOnes(idx) << 1 (please note the comment in aliasSameBasePointerGEPs regarding avoiding PR32314) also, if we have more than one array access, we can have: n - idx == m - idx then we have: n-m == 2*idx and so we can check: k...

In tracking down an alignment bug, I think I found a problem in ComputeMaskedBits. But I am not very well versed in this area of LLVM and need some more eyes. This is in the 2.3 release, though it looks like the relevant pieces operate the same way in trunk. I have the following add recurrence: %r849 = select i1 %r848, i64 0, i64 %r847 ; <i64> [#uses=10] %r862 = shl i64 %r849, 3 ;

Hello, This simple patch fixes PR9112: Index: lib/Analysis/ValueTracking.cpp =================================================================== --- lib/Analysis/ValueTracking.cpp (revision 125281) +++ lib/Analysis/ValueTracking.cpp (working copy) @@ -593,6 +593,8 @@ // Otherwise take the unions of the known bit sets of the operands, // taking conservative care to avoid

Hi all, Hi Eli, No, that appears to be something unrelated. I'm currently using revision 75246, while that patch only seems to apply to some later revision. Anyway, I actually located the real bug. Right at the end of InstCombiner::SimplifyDemandedUseBits, there's this piece of code: // If the client is only demanding bits that we know, return the known // constant. if

On Friday 18 July 2008 00:36, Nick Lewycky wrote: > David Greene wrote: > > Is my analysis correct? If so, is the PHI code the culprit (for not > > returning the min of the KnownZero bits) or is the Shl code the culprit > > (for not paying attention to the Mask passed in (it right shifts it)? > > I think your analysis is correct, and that Shl -- and many of the other

Hello All, I have met one may-alias case from llvm's alias analysis. The code snippet is as following: char buf[4]; void test (int idx) { char *a = &buf[3 - idx]; char *b = &buf[idx]; *a = 1; *b = 2; } I can see below output from alias set tracker for above code snippet. Alias sets for function 'test': Alias Set Tracker: 1 alias sets for 2 pointer values.  

David Greene wrote: > Is my analysis correct? If so, is the PHI code the culprit (for not returning > the min of the KnownZero bits) or is the Shl code the culprit (for not paying > attention to the Mask passed in (it right shifts it)? I think your analysis is correct, and that Shl -- and many of the other operations (AShr, LShr, SExt, Add?, Call?) -- should be modified to always

On Thu, Jul 30, 2009 at 5:57 AM, Nicolas Capens<nicolas at capens.net> wrote: > No, that appears to be something unrelated. I'm currently using revision > 75246, while that patch only seems to apply to some later revision. I don't see the connection... anyway, I can't easily help you with an old revision. > Anyway, I actually located the real bug. Right at the end of

Hi all, I'm instrumenting IR by replacing loads and stores by calls to a library, which I have compiled to bitcode such that inlining can take place. My problem is: If I could retain the alignment information on the load/store, this would open many optimization opportunities after inlining. Unfortunately, I don't know how. After thinking about it, and trying different things, I now

FYI, The CRC64 intrinsics were renamed to CRC32 since there is no such thing. See below for details. Chad On May 26, 2011, at 4:13 PM, Chad Rosier wrote: > Author: mcrosier > Date: Thu May 26 18:13:19 2011 > New Revision: 132163 > > URL: http://llvm.org/viewvc/llvm-project?rev=132163&view=rev > Log: > Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.

Hi Clemens, > I'm instrumenting IR by replacing loads and stores by calls to a library, which > I have compiled to bitcode such that inlining can take place. My problem is: If > I could retain the alignment information on the load/store, this would open many > optimization opportunities after inlining. Unfortunately, I don't know how. > > After thinking about it, and

Hi Duncan, thanks for your comments. >> First, consider this function: >> #include <stdint.h> >> uint64_t foo(uint64_t *bar) { >> *bar = 42; >> return (uint64_t)bar & 3; >> } >> >> Which is compiled to >> define i64 @foo(i64* %bar) nounwind uwtable ssp { >> store i64 42, i64* %bar, align 8 >>

Can someone explain what this function is supposed to do? I've looked at PowerPC, Sparc, etc.. and can't really figure out what I should be doing here. Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part

David Greene wrote: > On Friday 18 July 2008 00:36, Nick Lewycky wrote: >> David Greene wrote: >>> Is my analysis correct? If so, is the PHI code the culprit (for not >>> returning the min of the KnownZero bits) or is the Shl code the culprit >>> (for not paying attention to the Mask passed in (it right shifts it)? >> I think your analysis is correct, and

On Wed, Jul 29, 2009 at 3:45 AM, Nicolas Capens<nicolas at capens.net> wrote: > So could anyone who knows the ins and outs of this code have a look at how > to make it handle vectors correctly? Or if that’s not an option right now, > please revert the broken optimizations. Note that there might be more things > affected than visitAnd, visitOr and vistXor, I’ve only been able to

Hi Clemens, > thanks for your comments. > >>> First, consider this function: >>> #include <stdint.h> >>> uint64_t foo(uint64_t *bar) { >>> *bar = 42; >>> return (uint64_t)bar & 3; >>> } >>> >>> Which is compiled to >>> define i64 @foo(i64* %bar) nounwind uwtable ssp {

Hi All, I found a regression which triggers the asserts: "Binary operator types must match!" and "Op types should be identical!". It's happening with a piece of vector code, and the asserts happen because a logic operation is attempted between a vector and a scalar (which is not present in the original code, but created by InstCombine). It's caused by revision

Hi Andrew, Thank you for the suggestion. I've looked at CodeGenPrepare.cpp and MoveExtToFormExtLoad() is never run. I also notice that the ARM target produces the same additional register usage (copy) and zero extending (of the copy). (See the usage of r3 &r5 and also r12 & r4 in attached file arm-strcspn.s, my understanding is that 'ldrb' is zero extending.) Here is a

On Sep 10, 2013, at 8:59 AM, Robert Lytton <robert at xmos.com> wrote: > Hi, > > A bit more information. > I believe my problem lies with the fact that the load is left as 'anyext from i8'. > On the XCore target we know this will become an 8bit zext load - as there is no 8bit sign extended load! > If BB#1 were to force the load to a "zext from i8" would