Displaying 2 results from an estimated 2 matches for "knights_of_ni".
2017 Mar 11
2
Is there a way to know the target's L1 data cache line size?
...; Intel has stuck with 64 recently with x86, at least at L1. I believe
> multiple adjacent lines may be combined into a "block" (with a single
> tag) at L2 or higher in some of them.
>
> ARM can be 32 or 64.
>
>
>
> On Sat, Mar 11, 2017 at 3:24 PM, Hadrien G. <knights_of_ni at gmx.com
> <mailto:knights_of_ni at gmx.com>> wrote:
>
> I guess that in this case, what I would like to know is a
> reasonable upper bound of the cache line size on the target
> architecture. Something that I can align my data structures on at
> compil...
2017 Mar 11
3
Is there a way to know the target's L1 data cache line size?
I guess that in this case, what I would like to know is a reasonable
upper bound of the cache line size on the target architecture. Something
that I can align my data structures on at compile time so as to minimize
the odds of false sharing. Think
std::hardware_destructive_interference_size in C++17.
Le 11/03/2017 à 13:16, Bruce Hoult a écrit :
> There's no way to know, until you run