search for: kill

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2012 May 09
2
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
Hi, Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break: %vreg9<def> = IMPLICIT_DEF %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> => %vreg10<def> = IMPLICIT_DEF %vreg10:hi<def> = COPY %vreg1<kill> %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> =&g...
2009 Apr 22
2
[LLVMdev] Def/Kill flags for subregisters
I am trying to locate a bug that affects my Blackfin backend. I am having some trouble understanding the semantics of def/kill flags on machine operands when using subregisters. I compile this function: define void @i56_ls(i56 %x) nounwind { store i56 %x, i56* @i56_s ret void } And get this initial machine code: Live Ins: %R0 %R1 %reg1025D<def> = MOVE %R1 %reg1024D<def> = MOVE %R0 %reg1026D<def&g...
2015 Feb 19
2
[LLVMdev] ScheduleDAGInstrs computes deps using IR Values that may be invalid
...ve Ins: %X16 %X17 %X18 %X7 %X0 %X6 %X4 %W8 %X15 %X14 %W3 %W2 %X1 %X10 %X11 %X12 %X13 %X9 Predecessors according to CFG: BB#12 %X5<def> = ADDXrr %X16, %X13 * %W19<def> = LDRBBui %X5, 1; mem:LD1[%scevgep95](tbaa=<0x6e02518>) * %W3<def> = MADDWrrr %W2<kill>, %W3<kill>, %WZR * %W2<def> = SUBWrr %W3<kill>, %W19<kill> * STRBBui %W2<kill>, %X5<kill>, 1; mem:ST1[%scevgep95](tbaa=<0x6e02518>) Successors according to CFG: BB#16 BB#15: derived from LLVM BB %L20.1 Live Ins: %X16 %X17 %X18 %X7 %...
2014 Sep 05
5
[LLVMdev] [PATCH] [MachineSinking] Conservatively clear kill flags after coalescing.
On Sep 5, 2014, at 10:21 AM, Juergen Ributzka <juergen at apple.com> wrote: > clearKillFlags seems a little "overkill" to me. In this case you could just simply transfer the value of the kill flag from the SrcReg to the DstReg. We are extending the live-range of SrcReg. I do not see how you could relate that to the kill flag of DstReg. Therefore, I still think, this is the...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...= COPY %T1_W; R600_TReg32:%vreg17 %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14 %vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 %vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 %vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 %vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 %vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 %vreg23:sel_y<def> =...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...2:%vreg17 > %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 > %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 > %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14 > %vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 > %vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 > %vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 > %vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 > %vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 > %vreg2...
2010 Jul 28
3
[LLVMdev] Subregister coalescing
...INSERT_VECTOR_ELTs. Then we select those to INSERT_SUBREG, everything fine to that point. Status before live analisys is (non-related instrs removed): 36 %reg16388<def> = LDWr %reg16384, 0; mem:LD4[<unknown>] 68 %reg16392<def> = INSERT_SUBREG %reg16392<undef>, %reg16388<kill>, 1 76 %reg16394<def> = LDWr %reg16386<kill>, 0; mem:LD4[<unknown>] 116 %reg16400<def> = MOVEV %reg16392<kill> 124 %reg16400<def> = INSERT_SUBREG %reg16400, %reg16394<kill>, 2 132 %reg16401<def> = LDWr %reg16390<kill>, 0; mem:LD4[<unknown&...
2012 May 09
0
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
On May 9, 2012, at 6:27 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: > Hi, > > Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break: > > %vreg9<def> = IMPLICIT_DEF > %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi > %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> > => > %vreg10<def> = IMPLICIT_DEF > %vreg10:hi<def> = COPY %vreg1<kill> > %vreg12<def> = sub %vreg10<kill>...
2009 Apr 22
0
[LLVMdev] Def/Kill flags for subregisters
On Apr 22, 2009, at 12:03 AM, Jakob Stoklund Olesen wrote: > I am trying to locate a bug that affects my Blackfin backend. I am > having some trouble understanding the semantics of def/kill flags on > machine operands when using subregisters. > > I compile this function: > > define void @i56_ls(i56 %x) nounwind { > store i56 %x, i56* @i56_s > ret void > } > > And get this initial machine code: > > Live Ins: %R0 %R1 > %reg1025D<def> = MO...
2009 Jul 14
2
[LLVMdev] Kill-flag in two-address instruction tied operands
Hi, Two-address instructions are represented as normal three-address instructions with a Desc bit that indicates the first two operands are tied together. The question is, should the second operand have a <kill> flag? a: %R0<def> = MUL %R0, %R1<kill> b: %R0<def> = MUL %R0<kill>, %R1<kill> I think the current policy is a: There should be no kill-flag. The machine code verifier has code to handle the missing <kill> flag, and the regscavenger asserts if the <ki...
2012 May 14
1
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
...nk with IMPLICIT_DEF On May 9, 2012, at 6:27 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: Hi, Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break: %vreg9<def> = IMPLICIT_DEF %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> => %vreg10<def> = IMPLICIT_DEF %vreg10:hi<def> = COPY %vreg1<kill> %vreg12<def> = sub %vreg10<kill>, %vreg11<kill&gt...
2010 Sep 04
3
[LLVMdev] Possible missed optimization?
On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote: > I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer code, but since LLVM is so nearer to the optimal code sequence i wanted to reach it. In LLVM, copies are
2015 Feb 04
2
[LLVMdev] Handling of KILL instructions.
Hi all, My understanding is that we keep around KILL instructions in order to keep the results of the various register liveness analysis passes valid. Consider for example the following machine basic block: BB#0: derived from LLVM BB %entry Live Ins: %A0_64 %A1_64 %V0_64<def> = AND64 %A0_64<kill>, %A1_64<kill>...
2002 Jan 18
5
contrib/solaris/opensshd.in patch
This patch adds the seatbelts which _only_ kill parent sshd procs... -RMallory (eg: when you ssh into a machine and pkgadd the new openssh, it will not kill your current (or anyone else's sshd session) onanother_note: the buildpkg.sh could use some exec_prefix functionality... to deal with ./configure --prefix= --exec_prefix=/usr ***...
2017 Oct 09
4
{ARM} IfConversion does not detect BX instruction as a branch
...error seems to come from the IfConvertion MachinePass. Here's is what it looks like before and after. > #BEFORE IfConversion MachinePass > > BB#7: > Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12 > Predecessors according to CFG: BB#5 BB#6 > STRBi12 %R5, %R6<kill>, 0, pred:14, pred:%noreg; mem:ST1[%cond.i23.i.i.i] > %R6<def> = LDRBi12 %R7, 0, pred:14, pred:%noreg; mem:LD1[%15](align=4) > %R3<def> = EORri %R6, 254, pred:14, pred:%noreg, opt:%noreg > %R3<def> = ANDrr %R3<kill>, %R6<kill>, pred:14, pred:%noreg, opt:%...
2019 Nov 06
4
Possible Font problem with CentOS 7
Hi, I've got a possible font problem with a fully updated CentOS 7 system. An example with the man command. #man kill Should return the following KILL(1) User Commands KILL(1) NAME kill - terminate a process SYNOPSIS kill [-s signal|-p] [-q sigval] [-a] [--] pid... kill -l [signal] but what I actually get is the following KILL(1) User...
2014 Sep 05
3
[LLVMdev] [PATCH] [MachineSinking] Conservatively clear kill flags after coalescing.
Hi Quentin, Jonas looked further into the problem below, and asked me to submit his patch. Note the we have our own out-of-tree target, and we have not been able to reproduce this problem on an in-tree target. /Patrik Hägglund [MachineSinking] Conservatively clear kill flags after coalescing. This solves the problem of having a kill flag inside a loop with a definition of the register prior to the loop: %vreg368<def> ... Inside loop: %vreg520<def> = COPY %vreg368 %vreg568<def,tied1> = add %vreg341<tied0>, %vreg520<ki...
2010 Sep 05
2
[LLVMdev] Possible missed optimization?
...64 %a, i64 %b) nounwind readnone { entry: %xor = xor i64 %a, 18 ; <i64> [#uses=1] %xor2 = xor i64 %xor, %b ; <i64> [#uses=1] ret i64 %xor2 } produces these instructions before coalescing: 4L %reg16387<def> = COPY %R3<kill> 12L %reg16386<def> = COPY %R2<kill> 28L %reg16384<def> = COPY %R0<kill> 36L %reg16388<def> = COPY %reg16385<kill> 44L %reg16388<def>, %CPSR<def,dead> = tEOR %reg16388, %reg16387<kill>, pred:14, pred:%reg0 56L %reg16389&lt...
2018 Dec 13
5
dovecot/config processes one more time - which are safe to kill?
...fig processes never ending and spawning new one on each reload (https://www.dovecot.org/list/dovecot/2016-November/106058.html) is becoming a problem here: # ps aux|grep dovecot/config|wc -l 206 That's a lot of wasted memory - dovecot/config processes ate over 30GB of ram on 64GB box. Before killing dovecot/config processes: # free -m total used free shared buff/cache available Mem: 64437 61656 483 0 2297 after: # free -m total used free shared buff/cache available Mem: 64...