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Hi guys, I just noticed that the LLVM has some node for signed/unsigned type( like udiv, sdiv), but why the ADD, SUB do not have the counter part sadd, uadd? best kevin

Hi Guys, I and trying to covert a float to a f16. calling DAG.getNode(ISD::FP_ROUND, DL, Op->getValueType(0), FloatNode); will get the error message:"Invalid method to make FP_ROUND node" what is the "right" way to make this work? best Kevin -------------- next part -------------- An HTML attachment was scrubbed... URL:

So if the overflow happens for either one of the case, the return value will be implementation dependent? best kevin On Feb 17, 2015, at 2:01 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Kevin, > > On 17 February 2015 at 10:41, kewuzhang <kewu.zhang at amd.com> wrote: >> I just noticed that the LLVM has some node for signed/unsigned type( like udiv, sdiv), but why the ADD, SUB do not have the counter part sadd, uadd? > > That's because in 2s complement arithmetic the bit pattern of the > result doesn&...

Hi Guys, I see an intrinsic function call like this "call float @ir.sample_complex.f32(float a, int bitcast (i16 337203 to i32) , i32 1, <2 x float> %62, float %61) “, Then I got trouble to process the third operand "int bitcast (i16 337203 to i32)”, the second operand I got is “constant 337203”. I think something is messed up, but the getOperand(i) is llvm core function.

Hi guys, In X86ISelLowering.cpp I saw” ... case Intrinsic::x86_rdrand_16: case Intrinsic::x86_rdrand_32: …. case Intrinsic::x86_avx512_gather_qpd_512: case Intrinsic::x86_avx512_gather_qps_512: .. “ those intrinsics are handled by “LowerINTRINSIC_W_CHAIN”. How the “INTRINSIC_W_CHAIN” opCode is set instead of “INTRINSIC_WO_CHAIN”? tks Kevin -------------- next part -------------- An

...t. How can I make it to "access memory” so it will HasChain? Is there any flag set like in typeProfile, Node, instructions? myLoad, mayStore, SDNPHasChain? -kevin On Jul 18, 2014, at 4:26 PM, Tom Stellard <tom at stellard.net> wrote: > On Fri, Jul 18, 2014 at 04:15:45PM -0400, kewuzhang wrote: >> sure! >> >> class TEST_INTINSIC_FM< string asmstr> : Intrinsic >> <llvm_i32_ty], [llvm_i32_ty, llvm_ptr_ty], >> [IntrReadWriteArgMem], >> !strconcat(“llvm.test”, asmstr),”.float”) >> >; > > Have a look at the Selectio...

Hi Guys, In LLVM codegen, a typical binary operation instruction is defined something like below: " def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b), "xor.pred \t$dst, $a, $b;", [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>; “ which takes two inputs and write the result to the $dst register. Then how to define a binary

Hi All, In XCore backend, I saw “ …... EVT VT = Op.getValueType(); SDValue Data = DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3)); SDValue Crc(Data.getNode(), 1); SDValue Results[] = { Crc, Data }; return DAG.getMergeValues(Results, 2, DL); “ which is used to lower an

On Jul 31, 2014, at 7:23 PM, Tom Stellard <tom at stellard.net> wrote: > On Thu, Jul 31, 2014 at 06:41:06PM -0400, kewuzhang wrote: >> Hi All, >> >> Is it possible to initialize(set up) register attributes when we define an instruction? >> >> like >> >> if a register is defined like this: >> >> " class SC_Register<bits<8> register_num, >...

Hi Guys, I am trying to promote half to float for my intrinsic math operations, following class and pattern are defined. " class S_HF__HF< string asmstr> : Intrinsic <[llvm_float_ty ], [llvm_float_ty ], [IntrNoMem], !strconcat(asmstr, "_f16")>; def :Pat<( f16 (int_my_math_f16 f16:$src)), (F2Hsr (FEXTsr f16:$src) )>; “ where FEXTsr is

Hi guys, I am working on an intrinsic function, which will write to a pointer argument. So I am lowering it and think I need to catch it in lowerINTRINSIC_W_CHAIN, but somehow it always fall into INTRINSIC_WO_CHAIN category. I put [IntrReadwriteArgMem] into my Intrinsic class definition, it did not help. tried put [SDNPHasChain] into intrinsic class definition, cause errors” Element type

Hi Guys, I noticed that the operation actions( promote/expand/custom) are set per operation basis. Wondering if we can set it up globally? For example, I have native supported 32 bits registers, to handle 8 bits value operations, I want to do promote. and to support 64 bit operations, I want to expand. If I can set up the operation actions for the same type globally, then I can avoid to

..._W_CHAIN”? feel I missed something, but did not figure out. tks kevin On Jul 23, 2014, at 1:16 PM, Anton Korobeynikov <anton at korobeynikov.info> wrote: > Hello > > Chain operand is needed if the intrinsic is reading / writing memory. > > On Wed, Jul 23, 2014 at 8:02 PM, kewuzhang <kewu.zhang at amd.com> wrote: >> Hi guys, >> >> In X86ISelLowering.cpp >> >> I saw” >> ... >> case Intrinsic::x86_rdrand_16: >> case Intrinsic::x86_rdrand_32: >> …. >> case Intrinsic::x86_avx512_gather_qpd_512: >> cas...

...blem goes > away in my code. Is this just not a supported case currently? Or am I > doing something wrong? Wondering if there is any update about it? best kevin On Jun 16, 2014, at 5:08 PM, Cameron McInally <cameron.mcinally at nyu.edu> wrote: > On Mon, Jun 16, 2014 at 4:51 PM, kewuzhang <kewu.zhang at amd.com> wrote: >> Hi Guys, >> >> In LLVM codegen, >> a typical binary operation instruction is defined something like below: >> >> " def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b), >>...

Dear there, I have a target which is supporting the 32 bit operations natively. Right now,I want to make it support the 16 bits operations as well. My initial thought is: (1) I can adding something like “ CCIfType< [i16], CCPromoteToType<i32>>”, to the CallingConv.td, then “all” the 16 bits operands will be automatically promoted to 32 bits, it will be all set. but looks it is not

Hi Guys, I have a taget instruction which take a vec4 and returns a vec4.( say instruction “vec4:$dst mod( vec4:$src)" ) And I want to use it to match i an ir instruction/intrinsic function( say " float:$dst llvm.irmod( vec4:$src)" which takes a vec4, output a float. I think the procedure is: when I see the intrinsic llvm.irmod, I need to call "extractlt(

...it in lowering..) I think it doesn’t have chain in initial DAG. unfortunately the intrinsic “test.adddiv” is defined by me for now. not sure how to make it has a chain. kevin On Jul 18, 2014, at 3:06 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > On 7/18/2014 2:00 PM, kewuzhang wrote: >> >> I am working on an intrinsic function, which will write to a pointer argument. >> So I am lowering it and think I need to catch it in lowerINTRINSIC_W_CHAIN, but somehow it always fall into INTRINSIC_WO_CHAIN category. >> >> I put [IntrReadwriteArg...

Drear there: The problem I have is to lower an intrinsic function like this ” float @llvm.write.arg(flaot %src, float* %dst) “ I am lowering it with INTRINSIC_W_CHAIN, so the return value and the value to write to dst are generated with some operations using src: " // it is the frame index node corresponding to input pointer SDvalue frindex = Op.getoperand(3); … SDValue returnValue =

Hi guys, When I am trying to define pattern in a multi class, I got something like this: “ multi class P_PAT<string sty, SDNode tNode> { def : Pat<( !cast<ValueType>(“v2” # sty) (tNode !cast<ValueType>(“v2” # sty):$src1, !cast<ValueType>(“v2” # sty):$src2) ), ( add !cast<ValueType>(“v2” # sty):$src1, !cast<ValueType>(“v2” #

Dear Tom, What is the advantage to use the “pseudo instruction” approach VS “custom lowering/DAGtoDAGSelection” VS “ Library function”? Best Kevin On Aug 14, 2014, at 9:27 AM, Tom Stellard <tom at stellard.net> wrote: > On Thu, Aug 14, 2014 at 12:05:33AM -0700, Arsen Hakobyan wrote: >> Hi all, >> >> I would like to be sure that Tablegen still does not support