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On Wed, Jun 3, 2009 at 12:46 PM, Manjunath Kudlur<keveman at gmail.com> wrote: > Hello, > > I am writing a MachineFunction pass that converts vector instructions > to a sequence of scalar instructions. Why? That really isn't the level you want to be doing that sort of thing normally. Usually, legalization turns illegal vector operati...

I am seeing the following assertion in leak detector. /llvm/lib/VMCore/LeakDetector.cpp:43: void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"' failed. I am creating a list of instructions using BuildMI() and adding them to a basic block using BB->insert(). I am seeing this

On Wed, Jun 3, 2009 at 5:10 PM, Manjunath Kudlur <keveman at gmail.com> wrote: > I am seeing the following assertion in leak detector. > > /llvm/lib/VMCore/LeakDetector.cpp:43: > void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = > void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!&...

...Instrs(temp); for(unsigned i=0, e=temp.size(); i!=e; ++i) BB->insert(II, temp[i]); } I am getting the assertion during BB->insert() Manjunath On Wed, Jun 3, 2009 at 5:26 PM, Bill Wendling <isanbard at gmail.com> wrote: > On Wed, Jun 3, 2009 at 5:10 PM, Manjunath Kudlur <keveman at gmail.com> wrote: >> I am seeing the following assertion in leak detector. >> >> /llvm/lib/VMCore/LeakDetector.cpp:43: >> void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = >> void]: Assertion `Ts.count(Cache) == 0 && "Obj...

Hello, I am writing a MachineFunction pass that converts vector instructions to a sequence of scalar instructions. First, I go through the function and look for vector registers. For each vector register, I create a set of corresponding scalar registers using createVirtualRegister() function and put it in a map. Then I go through the function and replace vector instructions.The basic structure of

I am trying to JIT some code containing an indirect branch (and the corresponding store i8* blockaddress(@label)). I am using LLVM 2.7 code base. I build the ExecutionEngine using EngineBuilder, and call engine->getPointerToFunction(func). When I use setOptLevel(llvm::CodeGenOpt::None), the JITing fails with the following message : JIT.h:131: virtual void*

Hello, Given a TargetRegisterClass *RC, I was wondering if there is a way to find out what register class it is directly, instead of comparing it against all the &mytarget::Class1, &mytarget::Class2 etc. This goes back to my original intention of having special query functions for a subset of register classes. Suppose I wanted vector register classes (more than one, say 2-elements and

Hello, I am trying to convert the subtree (vector_shuffle v2f32, v2f32 (build_vector imm1, imm2)) to a machine instruction that takes 2 v2f32's and 2 immediates. I tried the following table gen pattern : (set v2f32Reg:$dst, (vector_shuffle v2f32Reg:$src1, v2f32Reg:$src2, (build_vector imm:$c1, imm:$c2))) Table gen barfs about type

Dan, > In general, it's a design goal to structure CodeGen features as > target-independent code parameterized with target-specific data. > The degree to which this goal is met in LLVM CodeGen features today > varies, but features that have been implemented using TableGen have > been relatively successful. Can you give an example of a relatively successful instance where

I was going through the function DAGTypeLegalizer::SplitVecRes_LOAD in LegalizeVectorTypes.cpp. I noticed that it is using getSizeInBits()/8 to compute IncrementSize, which is the offset for the load of second half of the vector. I have a situation where the frontend is producing load for a <2 x i1> type, and the architecture has i1 registers (but not v2i1 registers). The store size of i1 is

I noticed that the AsmWriter backend of TableGen is no longer handling the IMPLICIT_DEF case in printInstruction() function (by calling printImplicitDef). It was doing so in llvm 2.6. Is it supposed to be handled explicitly in printMachineInstruction()? What is the recommended method? Manjunath

Hello, I want to have an operation foo with variable number of operands, and I am trying to achieve it using multiple operations. Let's say I want to have [FOO r1, r2], I am constructing the DAG as follows : consumeArg(r1) -> consumeArg(r2) -> FOO -> arg(r1) -> arg(r2) Note that the arrows are all "Chain"s. I need to have consumeArg(r1) because, I don't want the

> All of the tablegen backends work this way. As you mentioned, > there are no target-specific tablegen backends at present. > > The underlying observation here is that features are never > fundamentally "specific for a target". For example, a mapping > between vector opcodes and associated scalar opcodes could > reasonably be made on many architectures. Even >

Hello, I am trying to create a machine instruction for "extractelement". I want to translate r <- extractelement v, 0 to mov r, v.x I was looking at the dag I can use and I found vector_extract. The inputs for this SDnode are a register and a iPtr constant. With that, I need to create 4 separate def's to extract element 0, 1, 2, and 3 and translate to v.x, v.y, v.z, and v.w. I

Christian, Thanks for your reply and the wiki entry. I did search the archives, but evidently I didn't search for the right thing. My bad. Anyways, I am still wondering about the other part of my question. Why aren't there Tablegen backends specific to some architecture backends? Let me describe a different scenario. Suppose my architecture has vector and scalar units, and suppose I want

I want to add a set of "properties" to each instruction in my instruction set, and want to be able to query that in my machine-specific optimizations. My Insts.td file looks as follows : class InstProperty; def propX : InstProperty; def propY : InstProperty; def propZ : InstProperty; class myInst<..., list<InstProperty> props> : Instruction { ... ...

Dan, Thanks a lot. Using a modifier in the assembly string works for this case. I am trying to solve a related problem. I am trying to print out a set of "mov" ops for the vector_shuffle node. Since the source of the "mov" is from one of the sources to vector_shuffle, depending on the mask, I am not sure what assembly string to emit. For example, if I have d <-