search for: karline

Displaying 20 results from an estimated 131 matches for "karline".

Did you mean: karlin
2017 Jun 21
0
customizing color key with plot3D
Karline, Thank you for your help. I discovered that in addition to including clim, I needed to omit breaks. This code uses one of your other examples as a starting point and works as intended: persp3D(z = volcano, zlim = c(-60, 200), phi = 20, colkey = list(length = 0.2, width = 0.4, shift = 0....
2001 Mar 27
1
username doesn't work
Hello. I've got samba 2.0.6. My smb.conf file contains: --------- [myhome] comment = My Home path = /home/myhome username = mary, jack read only = No -------- When I run: smbclient '//mycomputer/myhome' and type valid password for mary or jack. The answer is: -------- Password: session setup failed: ERRSRV - ERRbadpw (Bad password - name/password
2016 Oct 25
2
noveau: emergency shutdown handling is overcomplex and broken
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c index b9703c0..adb1deb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c @@ -120,6 +120,11 @@ nvkm_therm_sensor_event(struct nvkm_therm *therm, enum nvkm_therm_thrs thrs, struct work_struct *work; work =
2003 Mar 11
1
Data replication/migration
Hello. Does Samba or the CIFS protocol support files replication/migration? Regards Brain -------------------------------- Petr `Brain' Kulhavy <brain@artax.karlin.mff.cuni.cz> http://artax.karlin.mff.cuni.cz/~brain Faculty of Mathematics and Physics, Charles University Prague, Czech Republic --- A man without a woman is like a statue without pigeons.
2013 Nov 07
2
[LLVMdev] [PATCH] Do not generate nopl instruction on CPUs that don't support it.
On Tue, 5 Nov 2013, Rafael EspĂ­ndola wrote: > Please include a testcase with the patch. I'm sending testcase here. Compile it with "clang -O2 -march=k6-2 -c loop.c" > gas uses " nopl 0x0(%eax)" for k6_2. Are you sure it is a gas bug? Yes, it is gas bug. I should report it to binutils maintainers. Mikulas > On 3 November 2013 13:50, Mikulas Patocka >
2014 Sep 22
3
[LLVMdev] ARM assembler bug on LLVM 3.5
On Sun, 21 Sep 2014, Renato Golin wrote: > On 20 September 2014 15:19, Mikulas Patocka > <mikulas at artax.karlin.mff.cuni.cz> wrote: > > The problem is this - you either compile this program with > > -mcpu=cortex-a9, then clang reports error on the sdiv instruction because > > cortex a9 doesn't have sdiv. Or - you compile the program with > >
2018 May 24
2
[PATCH v3 11/27] x86/power/64: Adapt assembly for PIE support
On Wed 2018-05-23 12:54:05, Thomas Garnier wrote: > Change the assembly code to use only relative references of symbols for the > kernel to be PIE compatible. > > Position Independent Executable (PIE) support will allow to extended the > KASLR randomization range below the -2G memory limit. > > Signed-off-by: Thomas Garnier <thgarnie at google.com> Again, was this
2018 May 24
2
[PATCH v3 11/27] x86/power/64: Adapt assembly for PIE support
On Wed 2018-05-23 12:54:05, Thomas Garnier wrote: > Change the assembly code to use only relative references of symbols for the > kernel to be PIE compatible. > > Position Independent Executable (PIE) support will allow to extended the > KASLR randomization range below the -2G memory limit. > > Signed-off-by: Thomas Garnier <thgarnie at google.com> Again, was this
2018 May 24
2
[PATCH v3 09/27] x86/acpi: Adapt assembly for PIE support
On Wed 2018-05-23 12:54:03, Thomas Garnier wrote: > Change the assembly code to use only relative references of symbols for the > kernel to be PIE compatible. > > Position Independent Executable (PIE) support will allow to extended the > KASLR randomization range below the -2G memory limit. What testing did this get? > diff --git a/arch/x86/kernel/acpi/wakeup_64.S
2018 May 24
2
[PATCH v3 09/27] x86/acpi: Adapt assembly for PIE support
On Wed 2018-05-23 12:54:03, Thomas Garnier wrote: > Change the assembly code to use only relative references of symbols for the > kernel to be PIE compatible. > > Position Independent Executable (PIE) support will allow to extended the > KASLR randomization range below the -2G memory limit. What testing did this get? > diff --git a/arch/x86/kernel/acpi/wakeup_64.S
2018 May 25
2
[PATCH v3 09/27] x86/acpi: Adapt assembly for PIE support
On Thu 2018-05-24 09:35:42, Thomas Garnier wrote: > On Thu, May 24, 2018 at 4:03 AM Pavel Machek <pavel at ucw.cz> wrote: > > > On Wed 2018-05-23 12:54:03, Thomas Garnier wrote: > > > Change the assembly code to use only relative references of symbols for > the > > > kernel to be PIE compatible. > > > > > > Position Independent Executable
2018 May 25
2
[PATCH v3 09/27] x86/acpi: Adapt assembly for PIE support
On Thu 2018-05-24 09:35:42, Thomas Garnier wrote: > On Thu, May 24, 2018 at 4:03 AM Pavel Machek <pavel at ucw.cz> wrote: > > > On Wed 2018-05-23 12:54:03, Thomas Garnier wrote: > > > Change the assembly code to use only relative references of symbols for > the > > > kernel to be PIE compatible. > > > > > > Position Independent Executable
2013 Nov 12
0
[LLVMdev] [PATCH] Do not generate nopl instruction on CPUs that don't support it.
On 7 November 2013 18:31, Mikulas Patocka <mikulas at artax.karlin.mff.cuni.cz> wrote: > > > On Tue, 5 Nov 2013, Rafael EspĂ­ndola wrote: > >> Please include a testcase with the patch. > > I'm sending testcase here. Compile it with > "clang -O2 -march=k6-2 -c loop.c" The test should be in the patch itself. It can use llvm-mc to check how the nops are
2005 Nov 14
1
(no subject)
...his jacobian is 100*100. In the original package LSODA it is possible to specify that the jacobian is banded, which makes its inversion very efficient. However, this feature seems to have been removed in the R version. Is there a way to overcome this limitation? Thanks dr. Karline Soetaert NIOO - CEME PO box 140 4400 AC Yerseke the Netherlands Phone: ++ 31 113 577487 fax: ++ 31 113 573616 e-mail: k.Soetaert@nioo.knaw.nl [[alternative HTML version deleted]]
2018 May 29
1
[PATCH v3 09/27] x86/acpi: Adapt assembly for PIE support
On Fri 2018-05-25 10:00:04, Thomas Garnier wrote: > On Fri, May 25, 2018 at 2:14 AM Pavel Machek <pavel at ucw.cz> wrote: > > > On Thu 2018-05-24 09:35:42, Thomas Garnier wrote: > > > On Thu, May 24, 2018 at 4:03 AM Pavel Machek <pavel at ucw.cz> wrote: > > > > > > > On Wed 2018-05-23 12:54:03, Thomas Garnier wrote: > > > > >
2009 Apr 28
1
latticeExtra: useOuterStrips and axis.line$lwd
Hi, I'm working on some lattice wireframe figures that have two conditioning factors, and I want the strips labelled on the top and left of the entire plot, rather than above each individual panel. useOuterStrips() does this, but it draws internal axis lines, even after I explicitly set axis.line to 0. Is there a way to use useOuterStrips but without axis boxes? I've included a short
2013 Nov 05
0
[LLVMdev] [PATCH] Do not generate nopl instruction on CPUs that don't support it.
Please include a testcase with the patch. gas uses " nopl 0x0(%eax)" for k6_2. Are you sure it is a gas bug? On 3 November 2013 13:50, Mikulas Patocka <mikulas at artax.karlin.mff.cuni.cz> wrote: > Hi > > This patch fixes code generation bug - 586-class CPUs don't support the > nopl instruction and some 686-class CPUs don't support it too. > > I
2020 Jul 07
3
[RFC]: mm,power: introduce MADV_WIPEONSUSPEND
On Tue 07-07-20 10:07:26, Pavel Machek wrote: > Hi! > > > > > > This patch adds logic to the kernel power code to zero out contents of > > > > > all MADV_WIPEONSUSPEND VMAs present in the system during its transition > > > > > to any suspend state equal or greater/deeper than Suspend-to-memory, > > > > > known as S3. > > >
2020 Jul 07
3
[RFC]: mm,power: introduce MADV_WIPEONSUSPEND
On Tue 07-07-20 10:07:26, Pavel Machek wrote: > Hi! > > > > > > This patch adds logic to the kernel power code to zero out contents of > > > > > all MADV_WIPEONSUSPEND VMAs present in the system during its transition > > > > > to any suspend state equal or greater/deeper than Suspend-to-memory, > > > > > known as S3. > > >
2014 Sep 20
2
[LLVMdev] ARM assembler bug on LLVM 3.5
Hi I have the following ARM Linux program. The program detects if the processor has division instruction, if it does, it uses it, otherwise it uses slower library call. The program works with gcc, but it doesn't work with clang. clang reports error on the sdiv instruction in the assembler. The problem is this - you either compile this program with -mcpu=cortex-a9, then clang reports