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...your ARM board? Cheers Xerxes kapil anand skrev: > The Compilation error I am getting: > "Error while compiling ARMJITInfo.cpp.. > Selected processor does not support fstmfdd > sp!,{d0,d1,d2,d3,d4,d5,d6,d7}.... > > > > On Thu, Sep 24, 2009 at 8:45 PM, kapil anand <kapilanand2 at gmail.com > <mailto:kapilanand2 at gmail.com>> wrote: > > Hi all, > > I have an ARM virtual machine with ubuntu and want to port LLVM > over that. In release documents, ARM is not in the list of > supported platforms. I tried to compile LLVM on ARM p...

The Compilation error I am getting: "Error while compiling ARMJITInfo.cpp.. Selected processor does not support fstmfdd sp!,{d0,d1,d2,d3,d4,d5,d6,d7}.... On Thu, Sep 24, 2009 at 8:45 PM, kapil anand <kapilanand2 at gmail.com> wrote: > Hi all, > > I have an ARM virtual machine with ubuntu and want to port LLVM over that. > In release documents, ARM is not in the list of supported platforms. I tried > to compile LLVM on ARM platform and ran into an error. > > Has anyone tried to port...

Hi all, I have an ARM virtual machine with ubuntu and want to port LLVM over that. In release documents, ARM is not in the list of supported platforms. I tried to compile LLVM on ARM platform and ran into an error. Has anyone tried to port LLVM onto ARM before? Is it going to require lots of changes? Thanks --Kapil -------------- next part -------------- An HTML attachment was scrubbed...

...done with register allocation as a while "RegAllocBasic" was just put in, I hope this is looked at again. Do you have a working svn copy? Also, could you send me a copy/link to that '94 paper off the list please? -Thanks -Jeff Kunkel On Tue, Nov 2, 2010 at 6:57 PM, kapil anand <kapilanand2 at gmail.com> wrote: > Thanks Andrei! > > I haven't read the paper. I would see whether this fulfills my requirements > or whether I need to make any changes. > > --Kapil > > > On Tue, Nov 2, 2010 at 12:43 PM, Andrei Alvares <logytech at gmail.com>wrote: &gt...

...nand skrev: > > The Compilation error I am getting: > > "Error while compiling ARMJITInfo.cpp.. > > Selected processor does not support fstmfdd > > sp!,{d0,d1,d2,d3,d4,d5,d6,d7}.... > > > > > > > > On Thu, Sep 24, 2009 at 8:45 PM, kapil anand <kapilanand2 at gmail.com > > <mailto:kapilanand2 at gmail.com>> wrote: > > > > Hi all, > > > > I have an ARM virtual machine with ubuntu and want to port LLVM > > over that. In release documents, ARM is not in the list of > > supported platform...

...ink to that '94 paper off the list > please? > > You can get it from the following link: > http://ftp.cs.wisc.edu/pub/techreports/1994/TR1248.pdf > > Regards, > Andrei > > > -Thanks > > -Jeff Kunkel > > On Tue, Nov 2, 2010 at 6:57 PM, kapil anand <kapilanand2 at gmail.com> > wrote: > >> > >> Thanks Andrei! > >> > >> I haven't read the paper. I would see whether this fulfills my > >> requirements or whether I need to make any changes. > >> > >> --Kapil > >> > >> On...

...y and program profile analysis. In MICRO 27: Proceedings of the 27th annual international symposium on Microarchitecture. IEEE, 1994. Regards, Andrei On Tue, Nov 2, 2010 at 10:46 AM, Andrew Lenharth <andrewl at lenharth.org> wrote: > On Tue, Nov 2, 2010 at 12:28 AM, kapil anand <kapilanand2 at gmail.com> wrote: >> Hi all, >> >> Does LLVM infrastructure contain implementation of any static profiling >> algorithm apart from "Spill-Weight" calculation present in Live Intervals >> class? The future work page does suggest implementation of some &q...

...his release. > Also, could you send me a copy/link to that '94 paper off the list please? You can get it from the following link: http://ftp.cs.wisc.edu/pub/techreports/1994/TR1248.pdf Regards, Andrei > -Thanks > -Jeff Kunkel > On Tue, Nov 2, 2010 at 6:57 PM, kapil anand <kapilanand2 at gmail.com> wrote: >> >> Thanks Andrei! >> >> I haven't read the paper. I would see whether this fulfills my >> requirements or whether I need to make any changes. >> >> --Kapil >> >> On Tue, Nov 2, 2010 at 12:43 PM, Andrei Alvares <...

...CRO 27: Proceedings of the 27th annual > international symposium on Microarchitecture. IEEE, 1994. > > Regards, > Andrei > > On Tue, Nov 2, 2010 at 10:46 AM, Andrew Lenharth <andrewl at lenharth.org> > wrote: > > On Tue, Nov 2, 2010 at 12:28 AM, kapil anand <kapilanand2 at gmail.com> > wrote: > >> Hi all, > >> > >> Does LLVM infrastructure contain implementation of any static profiling > >> algorithm apart from "Spill-Weight" calculation present in Live > Intervals > >> class? The future work page doe...

...> please? >> >> You can get it from the following link: >>  http://ftp.cs.wisc.edu/pub/techreports/1994/TR1248.pdf >> >> Regards, >>  Andrei >> >> > -Thanks >> > -Jeff Kunkel >> > On Tue, Nov 2, 2010 at 6:57 PM, kapil anand <kapilanand2 at gmail.com> >> > wrote: >> >> >> >> Thanks Andrei! >> >> >> >> I haven't read the paper. I would see whether this fulfills my >> >> requirements or whether I need to make any changes. >> >> >> >> -...

On Wed, Aug 20, 2008 at 9:47 AM, kapil anand <kapilanand2 at gmail.com> wrote: > Hi, > > I have been working on implementing new analysis for a LLVM module. For > that, I need that Call Graph of the module. Inside the CallGraph file, the > constructor has been declared "protected" hence I can't define its instance > and...

On Wed, Jul 23, 2008 at 5:57 PM, kapil anand <kapilanand2 at gmail.com> wrote: > Hi, > > I was thinking about the ways to represent indirect branch in LLVM. It seems > that "Switch instruction" is the only way to logically represent indirect > branch inside LLVM. > Is there any other easier way to represent indirect branch i...

On Wed, Jul 23, 2008 at 8:47 PM, kapil anand <kapilanand2 at gmail.com> wrote: > > Specifically, I need a way to represent indirect branch instruction (in > binary) as an equivalent LLVM instruction. With switch instruction , I would > have to list all the possible targets and then initialize the corresponding > instruction. I was just t...

Just to make sure, can the label in a branch instruction be a "variable"? On Thu, Jul 24, 2008 at 12:08 AM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Wed, Jul 23, 2008 at 8:47 PM, kapil anand <kapilanand2 at gmail.com> > wrote: > > > > Specifically, I need a way to represent indirect branch instruction (in > > binary) as an equivalent LLVM instruction. With switch instruction , I > would > > have to list all the possible targets and then initialize the > correspon...

On Tue, Nov 2, 2010 at 12:28 AM, kapil anand <kapilanand2 at gmail.com> wrote: > Hi all, > > Does LLVM infrastructure contain implementation of any static profiling > algorithm apart from "Spill-Weight" calculation present in Live Intervals > class? The future work page does suggest implementation of some "static > prof...

Hi, I was thinking about the ways to represent indirect branch in LLVM. It seems that "Switch instruction" is the only way to logically represent indirect branch inside LLVM. Is there any other easier way to represent indirect branch in LLVM? Thanks Kapil -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, I have been working on implementing new analysis for a LLVM module. For that, I need that Call Graph of the module. Inside the CallGraph file, the constructor has been declared "protected" hence I can't define its instance and thus use the CallGraph for further analysis. So, what are the ways of building and using Call Graph of a module. Do I need to make my new analysis as

Hi all, Does LLVM infrastructure contain implementation of any static profiling algorithm apart from "Spill-Weight" calculation present in Live Intervals class? The future work page does suggest implementation of some "static profiling" algorithms to make an educated guesses about the relative execution frequencies of various parts of the code. Thanks --Kapil --------------

...hether it might be possible to have some kind of indirect branch where label is a "variable" and not an explicit label present in module. -Kapil On Wed, Jul 23, 2008 at 10:36 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Wed, Jul 23, 2008 at 5:57 PM, kapil anand <kapilanand2 at gmail.com> > wrote: > > Hi, > > > > I was thinking about the ways to represent indirect branch in LLVM. It > seems > > that "Switch instruction" is the only way to logically represent indirect > > branch inside LLVM. > > Is there any other e...

On Wed, Jul 2, 2008 at 10:07 AM, kapil anand <kapilanand2 at gmail.com> wrote: > Hi, > > I am using various LLVM optimization passes and I noticed a strange > behaviour in Mem2Reg Optimization. These pass is used for SSA construction > and basically removed alloca of the corresponding pointers are just used in > load/stores. > So,...