Displaying 10 results from an estimated 10 matches for "kalimba".
2014 Jul 10
2
[LLVMdev] [PATCH][REQUEST] Could someone submit this CSR Kalimba definitions patch please?
...endian 32-bit CPU (PNaCl /
Emscripten)
amdil, // amdil: amd IL
spir, // SPIR: standard portable IR for OpenCL 32-bit version
- spir64 // SPIR: standard portable IR for OpenCL 64-bit version
+ spir64, // SPIR: standard portable IR for OpenCL 64-bit version
+ kalimba // Kalimba: generic kalimba
};
enum VendorType {
UnknownVendor,
@@ -89,7 +90,8 @@
Freescale,
IBM,
ImaginationTechnologies,
- NVIDIA
+ NVIDIA,
+ CSR
};
enum OSType {
UnknownOS,
Index: lib/Support/Triple.cpp
==================================...
2014 Jul 09
5
[LLVMdev] [PATCH][REQUEST] Could someone submit this CSR Kalimba definitions patch please?
...patch request to the llvm-commits list requesting
that someone could apply a patch to Triple.h and Triple.cpp for me. I
didn't get any response so I wondered whether I should have posted to
this list instead.
My story is as follows: we are trying to get lldb/llvm support for CSRs
range of Kalimba DSPs. Eventually we are planning to hire someone to
write an LLVM backend for the core, but currently we/I are making to do
with porting lldb to debug Kalimba chips via a bespoke gdbserver
implementation.
In order to get lldb to recognise Kalimba DSPs I have had to add
definitions for kalimba...
2014 Jul 09
2
[LLVMdev] [PATCH][REQUEST] Could someone submit this CSR Kalimba definitions patch please?
On 7/9/14, 12:33 PM, Eric Christopher wrote:
> Any reason why you deleted code that isn't related?
>
> -eric
>
>> - enum SubArchType {
>> - NoSubArch,
>> -
>> - ARMSubArch_v8,
>> - ARMSubArch_v7,
>> - ARMSubArch_v7em,
>> - ARMSubArch_v7m,
>> - ARMSubArch_v7s,
>> - ARMSubArch_v6,
>> -
2015 Sep 01
0
Anyone ports Opus to CSR Kalimba DSP?
Hi All,
Wondering if you or you know some one has done the porting from Opus C
reference design to the Assembly of CSR Kalimba DSP? We are working porting
and would like to ask more people ( consultant) to join the effort.
Thanks,
Z
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2008 Nov 23
1
Speex DSP porting
Hello Developers,
I am considering using SPEEX on an embedded processor that is in fact a
DSP with fixed point
24 bit resolution. This DSP is named 'Kalimba' and is present in CSR's
product:
BLUECORE5.
I'm very interested if anybody can tell me if porting is possible (in
fact if there are sufficient resources) for implementing a real-time
encoding-decoding (duplex). I'm interested in 4kbps bitrate.
Any help will be greatly apprecia...
2014 Sep 09
2
[LLVMdev] Machine Code for different architectures
Hi,
We have some DSP architectures (kalimba) which have 24-bits as their
"minimum addressable unit". So this means that the sizeof a char (and
an int and a short for that matter) is 24-bits.
I quickly read the posted link WritingAnLLVMBackend.html but did not
see an obvious answer to the following question:
Is it possible to writ...
2014 Sep 09
3
[LLVMdev] Machine Code for different architectures
...lso unsure how hard byte=8bits is backed into Clang. You might
> want to ask cfe-dev.
>
> I hope that helps.
>
> Johnny
>
> On Tue, Sep 9, 2014 at 7:41 AM, Matthew Gardiner <mg11 at csr.com> wrote:
>
> > Hi,
> >
> > We have some DSP architectures (kalimba) which have 24-bits as their
> > "minimum addressable unit". So this means that the sizeof a char
> > (and an int and a short for that matter) is 24-bits.
> >
> > I quickly read the posted link WritingAnLLVMBackend.html but did not
> > see an obvious answer t...
2014 Sep 10
2
[LLVMdev] Machine Code for different architectures
...u might
> > want to ask cfe-dev.
> >
> > I hope that helps.
> >
> > Johnny
> >
> > On Tue, Sep 9, 2014 at 7:41 AM, Matthew Gardiner <mg11 at csr.com> wrote:
> >
> > > Hi,
> > >
> > > We have some DSP architectures (kalimba) which have 24-bits as their
> > > "minimum addressable unit". So this means that the sizeof a char
> > > (and an int and a short for that matter) is 24-bits.
> > >
> > > I quickly read the posted link WritingAnLLVMBackend.html but did not
> > >...
2015 Apr 15
2
[LLVMdev] About the "debugger target"
While I've already posted reviews for the initial patches for this (see
http://reviews.llvm.org/D8506 and http://reviews.llvm.org/D8599), the
grapevine suggests I should post a lengthier description of my intent
for the "debugger target." The idea was prompted by a suggestion from
Eric Christopher, and I'm running with it.
Various bits of the DWARF we produce are conditional on
2014 Sep 09
2
[LLVMdev] Machine Code for different architectures
How does LLVM generate machine code for different architectures?
For example, the machine code for x86 and amd will vary.
How does LLVM convert its IR to machine code for different
architectures.Can you please explain the approach? Is it just write two
different programs for two different architectures and pass a flag to the
compiler based on which machine code you want to generate?
Thanks a lot