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2016 May 10
2
Atomic LL/SC loops in llvm
Replied too early... Below:
On Tue, May 10, 2016 at 2:04 PM, JF Bastien <jfb at google.com> wrote:
> Thanks for the writeup, that is indeed pretty ugly. Simple
> asm(:::"memory") isn't sufficient either, since the regalloc can decode to
> spill :-(
>
> On Tue, May 10, 2016 at 12:22 PM, James Knight via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
2016 May 10
4
Atomic LL/SC loops in llvm
...ly problematic.)
5. Execute only a small number of instructions within the loop.
That last restriction seems most odd as a hard constraint, as opposed to just a performance win. It is apparently because a common implementation <http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka8404.html> is for the LL instruction to pull the cache-line local, and invalidate it from all remote caches (as if the LL were actually a write). The subsequent SC will then succeed only if the cacheline has not been invalidated since the LL. With a naive implementation, LL operations on two CPUs exe...