search for: k1om

...ing.cpp.o [ 88%] Building CXX object lib/Target/X86/CMakeFiles/LLVMX86CodeGen.dir/X86InstrInfo.cpp.o [ 88%] Building CXX object lib/Target/X86/CMakeFiles/LLVMX86CodeGen.dir/X86JITInfo.cpp.o /tmp/icpcI3Tb9Aas_.s: Assembler messages: /tmp/icpcI3Tb9Aas_.s:48: Error: `movaps' is not supported on `k1om' /tmp/icpcI3Tb9Aas_.s:49: Error: `movaps' is not supported on `k1om' /tmp/icpcI3Tb9Aas_.s:50: Error: `movaps' is not supported on `k1om' /tmp/icpcI3Tb9Aas_.s:51: Error: `movaps' is not supported on `k1om' It seems LLVM JIT for KNC is new territory.Can the JIT be used on...

Hi, We have the same difficulties. KNC (dubbed k1om in compiler utils) is a 64-bit device with 8087-compatible scalar arithmetics and non-standard vector arithmetics. More specifically, the widely used variant of 64-bit ABI implemented by LLVM involves xmm registers, while KNC does not have xmm-s and instead has zmm-s (512-bit wide). This makes stan...

Hello Elena, > There is no 32-bit KNC. Are you sure about this? From "System V Application Binary Interface K1OM Architecture Processor Supplement Version 1.0", p. 124: | A.1 Execution of 32-bit Programs | | The K1OM processors are able to execute 64-bit K1OM and also 32-bit ia32 programs. I'm really really looking for this opportunity, because we want to extend our kernel code generation capabilit...

...at could be done with current LLVM trunk to deliver basic Intel MIC support. Let's say, for basic level we'd want just scalar code execution, no threading, no zmm vectors. Attached verbose in text, but functionally very simple patch copy-pastes x86 and x86_64 backends into 32-bit and 64-bit K1OM. In the end of the message you can find how simple LLVM-generated programs could be compiled & executed on MIC device, using this patch. Could you please help finding answers to the following questions: 1) Is there actually a 32-bit mode for MIC? 32-bit ELFs are not recognized, so... 2) MIC I...

...uld be done with current LLVM trunk to deliver basic Intel MIC support. Let's say, for basic level we'd want just scalar code execution, no threading, no zmm vectors. > Attached verbose in text, but functionally very simple patch copy-pastes x86 and x86_64 backends into 32-bit and 64-bit K1OM. In the end of the message you can find how simple LLVM-generated programs could be compiled & executed on MIC device, using this patch. > > Could you please help finding answers to the following questions: > > 1) Is there actually a 32-bit mode for MIC? 32-bit ELFs are not recogniz...

...uld be done with current LLVM trunk to deliver basic Intel MIC support. Let's say, for basic level we'd want just scalar code execution, no threading, no zmm vectors. > Attached verbose in text, but functionally very simple patch copy-pastes x86 and x86_64 backends into 32-bit and 64-bit K1OM. In the end of the message you can find how simple LLVM-generated programs could be compiled & executed on MIC device, using this patch. > > Could you please help finding answers to the following questions: > > 1) Is there actually a 32-bit mode for MIC? 32-bit ELFs are not recogniz...

...at could be done with current LLVM trunk to deliver basic Intel MIC support. Let's say, for basic level we'd want just scalar code execution, no threading, no zmm vectors. Attached verbose in text, but functionally very simple patch copy-pastes x86 and x86_64 backends into 32-bit and 64-bit K1OM. In the end of the message you can find how simple LLVM-generated programs could be compiled & executed on MIC device, using this patch. Could you please help finding answers to the following questions: 1) Is there actually a 32-bit mode for MIC? 32-bit ELFs are not recognized, so... 2) MIC I...