search for: k10

...ies Inc SBx00 Azalia (Intel HDA) 00:14.3 ISA bridge: ATI Technologies Inc SB700/SB800 LPC host controller 00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge 00:14.5 USB Controller: ATI Technologies Inc SB700/SB800 USB OHCI2 Controller 00:18.0 Host bridge: Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices...

Hi All, I'm trying to get lm_sensors to work on a Shuttle with an AMD K10. The version of lm_sensors in the main CentOS repo is 2.10.7, which is two years old now. Support for the K10 was added about a year ago. So, does anyone know if there are binaries available for more recent versions of lm_sensors? Also, if anyone has knowledge of the sensors layout for recent Shu...

...gies Inc SBx00 Azalia (Intel HDA) 00:14.3 ISA bridge: ATI Technologies Inc SB700/SB800 LPC host controller 00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge 00:14.5 USB Controller: ATI Technologies Inc SB700/SB800 USB OHCI2 Controller 00:18.0 Host bridge: Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AM...

...3.6282 ( 18.9%) Combine redundant instructions 1.2138 ( 6.4%) 0.0040 ( 5.0%) 1.2178 ( 6.4%) 1.2185 ( 6.4%) SROA ... real 1m7.783s user 1m7.548s sys 0m0.183s So: opt reports that it took 19 seconds, but overall, the run took 88 seconds. The system in question is a 6-core AMD K10 with 8GB of memory. The system is not running anything else at the time. What activity accounts for the unaccounted-for time? For my application, IR verification has pathological performance (I ought to file a bug on that), therefore I disable it. It is not clear if the IR verifier is running in...

...Bridge (rev 40) 00:14.5 USB Controller: ATI Technologies Inc SB700/SB800 USB OHCI2 Controller 00:16.0 USB Controller: ATI Technologies Inc SB700/SB800 USB OHCI0 Controller 00:16.2 USB Controller: ATI Technologies Inc SB700/SB800 USB EHCI Controller 00:18.0 Host bridge: Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AM...

...wn. Use 'virsh shutdown' on each of the guests first and then shutdown the host. Use autostart to restart guests on a host's reboot. Write a script to process 'virsh list' to feed active domains to 'virsh shutdown' if automation is required and link that to /etc/rc0.d/K10<whatever>. 2. In the situation where a kvm guest pause and restore sequence leads to an excessive disconnect between guest time and wall time use ntpd -q to hard set the time. From the guest's point of view you are always going ahead in time in the case of a pause and resume so this is...

To the Linux Community at Large: I reported to this list back in January, 2010 that the standard x86_64 kernel, when built from the src.rpm and modified for AMD K8 / K10 Extensions would not build. I reported this here and to Red Hat via Bugzilla ID number 558367. RH AS / Centos 5.3 worked fine. That was Centos 5.4 / Red Hat Enterprise AS 5 Update 4. Today we tried to optimize Red Hat Enterprise AS 5 Update 5. Same problem. At last check all kernels from 2.6.1...

Hello, I am building a home file server and am looking for an ATX mother board that will be supported well with OpenSolaris (onboard SATA controller, network, graphics if any, audio, etc). I decided to go for Intel based boards (socket LGA 775) since it seems like power management is better supported with Intel processors and power efficiency is an important factor. After reading several

Hello, I''ve successfully passed a unmodified GTX 760 to Win7 x64. It involved some driver patching on the client side but I''m close to getting the required steps on the server side, too. Are there any legal issues that might arise from releasing a patch? Bob [image: Inline image 1] _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org

...mp_init(1000); > >   mp_rand_n(a, 1000); >   mp_rand_n(b, 1000); > >   for (i = 0; i < 2400000; i++) >      mp_add_nc(c, a, b, 1000); > >   return 0; > } > > Ignore all of it except the mp_add_nc function. Now this runs at 4 > cycles per int64 addition on AMD K10. If I fiddle a bit and loop > unroll, I get 2.5 cycles. But optimal is actually 1.6 cycles. > > The part of the loop in question becomes: > > %tmp.i = add i64 %indvar.i, 1                   ; <i64> [#uses=2] >  %22 = load i64* %scevgep.i, align 8             ; <i64> [#...

...a = mp_init(1000); b = mp_init(1000); c = mp_init(1000); mp_rand_n(a, 1000); mp_rand_n(b, 1000); for (i = 0; i < 2400000; i++) mp_add_nc(c, a, b, 1000); return 0; } Ignore all of it except the mp_add_nc function. Now this runs at 4 cycles per int64 addition on AMD K10. If I fiddle a bit and loop unroll, I get 2.5 cycles. But optimal is actually 1.6 cycles. The part of the loop in question becomes: %tmp.i = add i64 %indvar.i, 1 ; <i64> [#uses=2] %22 = load i64* %scevgep.i, align 8 ; <i64> [#uses=1] %23 = zext i64 %2...

Hi, When KVM's check_cr_write() is invoked to write to %cr3, it tests that the lower three bits of %cr3 are set to zero. On real h/w (tested on Core2, K10), these bits are ignored; the AMD64 documentation describes the bits as 'should', but not 'must' be zero. The Intel documentation seems to indicate that the bits are ignored as well. I don't know whether to call this a bug or not, but it is a divergence from real h/w. Thanks,...

Hi, When KVM's check_cr_write() is invoked to write to %cr3, it tests that the lower three bits of %cr3 are set to zero. On real h/w (tested on Core2, K10), these bits are ignored; the AMD64 documentation describes the bits as 'should', but not 'must' be zero. The Intel documentation seems to indicate that the bits are ignored as well. I don't know whether to call this a bug or not, but it is a divergence from real h/w. Thanks,...

...00); >> mp_rand_n(b, 1000); >> >> for (i = 0; i < 2400000; i++) >> mp_add_nc(c, a, b, 1000); >> >> return 0; >> } >> >> Ignore all of it except the mp_add_nc function. Now this runs at 4 >> cycles per int64 addition on AMD K10. If I fiddle a bit and loop >> unroll, I get 2.5 cycles. But optimal is actually 1.6 cycles. >> >> The part of the loop in question becomes: >> >> %tmp.i = add i64 %indvar.i, 1 ; <i64> [#uses=2] >> %22 = load i64* %scevgep.i, align 8...

I have been seeing something for quite some time which has confused me considerably for over a year, perhaps one of you can help me understand. Assumed: rpm queries are against _a_ database. Assumed: database queries against the same database, without changes to the data in the database, will return the same data. Confusion: then why are some of the summaries reported by rpm different? Each day

...); >>> >>>   for (i = 0; i < 2400000; i++) >>>      mp_add_nc(c, a, b, 1000); >>> >>>   return 0; >>> } >>> >>> Ignore all of it except the mp_add_nc function. Now this runs at 4 >>> cycles per int64 addition on AMD K10. If I fiddle a bit and loop >>> unroll, I get 2.5 cycles. But optimal is actually 1.6 cycles. >>> >>> The part of the loop in question becomes: >>> >>> %tmp.i = add i64 %indvar.i, 1                   ; <i64> [#uses=2] >>>  %22 = load i64*...

..."i3", "i4", "i5", "i6", "i7", "i8", "i9", "j1", "j10", "j2", "j3", "j4", "j5", "j6", "j7", "j8", "j9", "k1", "k10", "k2", "k3", "k4", "k5", "k6", "k7", "k8", "k9", "l1", "l10", "l11", "l12", "l2", "l3", "l4", "l5", "l6", "l...

On Fri, Jun 11, 2010 at 3:28 PM, Bill Hart <goodwillhart at googlemail.com> wrote: > Hi Eli, > > On 11 June 2010 22:44, Eli Friedman <eli.friedman at gmail.com> wrote: >> On Fri, Jun 11, 2010 at 10:37 AM, Bill Hart <goodwillhart at googlemail.com> wrote: >>> a) What plans are there to support addition, subtraction, >>> multiplication, division,

Hi Gordan, I received my Asus GTX 480 today (bought on ebay). Finally I succeeded in - quadrifying my GTX 480  into a Quadro 6000 ( softmod). - overpassing the 3-4GB of RAM on Windows XP 64 bits (domU) by applying a well known patch for Xen. - playing Crysis 2 and Darksiders II for a few minutes. http://img11.hostingpics.net/pics/953254ScreenshotXenSoftModedQuadro6000.png Using nvlfash I

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