Displaying 20 results from an estimated 24 matches for "jyotsna".
2012 Aug 28
4
[LLVMdev] TableGen backend support to express relations between instruction
...on mapping tables. Please take a look and let me know your
suggestions. As of now, I create one mapping table per relation which
results into a long .inc file. So, I'm planning to combine everything into a
single table and will include APIs (one per relation) to query from this
table.
Thanks,
Jyotsna
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Jyotsna Verma
Sent: Tuesday, August 21, 2012 12:42 PM
To: 'Jakob Stoklund Olesen'
Cc: llvmdev at cs.ui...
2012 Aug 31
0
[LLVMdev] TableGen backend support to express relations between instruction
Hi Jakob,
Did you get a chance to look at the patch?
Thanks,
Jyotsna
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Jyotsna Verma
Sent: Tuesday, August 28, 2012 1:01 PM
To: 'Jakob Stoklund Ol...
2012 Aug 28
0
[LLVMdev] TableGen backend support to express relations between instruction
Jyotsna,
I hadn't been following this, so I apologize if this has already been
provided, but can you give a quick example of how this functionality is
used?
Thanks in advance,
Hal
On Tue, 28 Aug 2012 13:01:17 -0500
"Jyotsna Verma" <jverma at codeaurora.org> wrote:
> Hi Jakob,
>...
2012 Aug 28
1
[LLVMdev] TableGen backend support to express relations between instruction
...s a table which can be
queried using a function
getPredOpcode(Opcode, predsense) {
If (predsense == true)
return getPredOpcodeTable[Opcode][0]
if (predsense == false)
return getPredOpcodeTable[Opcode][1]
}
Let me know if something is not clear and I will try to explain it further.
Thanks,
Jyotsna
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
-----Original Message-----
From: Hal Finkel [mailto:hfinkel at anl.gov]
Sent: Tuesday, August 28, 2012 1:27 PM
To: Jyotsna Verma
Cc: 'Jakob Stoklund Olesen'; llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] TableGen backe...
2013 Mar 11
2
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
Hi There,
We want to disable all ExecutionEngine JIT/MCJIT tests
(llvm/unittests/ExecutionEngine) for Hexagon. I have been looking into the
test framework but haven't quite figured out how to turn them off. We cross
compile Hexagon on X86 and are not interested in JIT support.
Thanks,
Jyotsna
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
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2013 Mar 11
0
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
Hi Jyotsna,
Currently there's a preprocessor trick that prevents llvm/unittests/ExecutionEngine/MCJIT tests from running on architectures and operating systems that are known to fail.
Specifically, check out the functions OSSupportsMCJIT() and ArchSupportsMCJIT() functions in unittests/ExecutionEngine/M...
2012 Aug 20
2
[LLVMdev] TableGen related question for the Hexagon backend
You're right. I can have use RowFields for that purpose.
Thanks,
Jyotsna
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk]
Sent: Monday, August 20, 2012 3:42 PM
To: Jyotsna Verma
Cc: 'Tony Linthicum'; llvmdev at cs.uiuc.edu
Subject: Re: TableGen related que...
2013 Mar 13
2
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
...ppears to me that these tests will always fail for
cross-compilation unless modified for remote execution.
I noticed "TARGET_HAS_JIT" flag in Makefile.config. Can I use this flag to
exclude MCJIT and JIT tests when not set? This will be a simpler change than
modifying the macro.
Thanks,
Jyotsna
2012 Aug 21
0
[LLVMdev] TableGen related question for the Hexagon backend
Jakob,
One more question. You had suggested 'ValueCols' as of type
list<list<string> >. Does the TableGen know how to extract it? It appears to
me that we may have to add support for that.
Thanks,
Jyotsna
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Jyotsna Verma
Sent: Monday, August 20, 2012 3:59 PM
To: 'Jakob Stoklund Olesen'
Cc: llvmdev at cs.uiuc...
2013 Mar 12
2
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
...from the
supported arch list but didn't see any effect.
I was just wondering if these tests are meant to work for any of the
cross-compiled targets. If not, then we can probably enable them only when
Host and Target Triples are same and the host architecture is in the
supported list.
Thanks,
Jyotsna
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
>-----Original Message-----
>From: Malea, Daniel [mailto:daniel.malea at intel.com]
>Sent: Monday, March 11, 2013 2:52 PM
>To: Jyotsna Verma; llvmdev at cs.uiuc.edu
>Subject: Re: [...
2013 Mar 13
0
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
On 2013-03-13 3:15 AM, "Jyotsna Verma" <jverma at codeaurora.org> wrote:
>
>I noticed "TARGET_HAS_JIT" flag in Makefile.config. Can I use this flag to
>exclude MCJIT and JIT tests when not set? This will be a simpler change
>than
>modifying the macro.
>
>Thanks,
>Jyotsna
TARGET_HAS_...
2012 Aug 21
1
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 20, 2012, at 9:22 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
> Jakob,
>
> One more question. You had suggested 'ValueCols' as of type
> list<list<string> >. Does the TableGen know how to extract it? It appears to
> me that we may have to add support for that.
You just start f...
2012 Aug 20
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 20, 2012, at 1:32 PM, "Jyotsna Verma" <jverma at codeaurora.org> wrote:
> In the Hexagon backend, a predicated instruction can translate into another
> form called 'predicate new'. So, in our example of 'ADD', we can have
> another transformation like this -
>
> ADD--- ---> ADDtrue...
2012 Aug 20
2
[LLVMdev] TableGen related question for the Hexagon backend
...;
}
def ADDtrue_new {
let BaseOpcode = "ADD";
let PredSense = "true";
let DotNewType = "new";
}
This allows me to list all the attributes that must remain same between the
Key column and the related instructions. Let me know what you think about
this.
Thanks,
Jyotsna
> > Are you saying that the mechanism is already present which allows us
> > to relate instructions with each other? What do you mean by a proper
> > query language?
>
> Yes, in the very simple sense that you can relate instructions that have
the
> same value in a field...
2012 Aug 16
2
[LLVMdev] TableGen related question for the Hexagon backend
...rom a subclass are eventually added into the
instruction record -- existing functionality
6) Add a new command line option into TableGen that will emit this
information as a table in a .inc file.
7) Target is required to add its own API to read the table and extract
relevant information.
Thanks,
Jyotsna
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk]
Sent: Thursday, August 02, 2012 5:24 PM
To: Jyotsna Verma
Cc: 'Tony Linthicum'; llvmdev at cs.uiuc.edu
Subject: Re: TableGen related qu...
2013 May 03
1
[LLVMdev] buildbot failure in LLVM on llvm-ppc64-linux1
...k dump problem.
I tried to configure and build LLVM for PowerPC on my machine locally but don't see the failures. I had to remove '-maltivec' from tools/clang/lib/Lex/Makefile or else it wouldn't build for me.
Any help to reproduce the problem will be greatly appreciated!
Thanks,
Jyotsna
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>-----Original Message-----
>From: llvm.buildmaster at lab.llvm.org [mailto:llvm.buildmaster at lab.llvm.org]
>Sent: Thursday, May 02, 2013 4:51 PM
>To: Jyotsna Verma
>Cc: gkistanov...
2012 Aug 17
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 16, 2012, at 1:39 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
> Hi Everyone,
>
> After some more thoughts to the Jacob's suggestion of using multiclasses for
> Opcode mapping, this is what I have come up with. Please take a look at the
> design below and let me know if you have any suggestions...
2012 Aug 01
3
[LLVMdev] TableGen related question for the Hexagon backend
...{HexagonISD::ADDrr, HexagonISD::ADDrr, HexagonISD:: ADDrr_p,
HexagonISD::ADDrr_np}, {HexagonISD::ADDrr_p, HexagonISD::ADDrr, -1, -1},
{HexagonISD::ADDrr_np, HexagonISD::ADDrr, -1, -1}, .
};
Each column represents a specific relationship, -1 means
'invalid/nonexistent relation'.
Thanks,
Jyotsna
-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Tony Linthicum
Sent: Monday, May 14, 2012 11:10 AM
To: Jakob Stoklund Olesen
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r156634 - in /llvm/trunk:
l...
2012 Aug 02
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
>
> Currently, we rely on switch tables to transform between formats. However,
> we would like to have a different mechanism to represent these relationships
> instead of switch tables. I am thinking of modeling these relations in
> Hexa...
2013 Mar 12
0
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
On 2013-03-12 1:28 AM, "Jyotsna Verma" <jverma at codeaurora.org> wrote:
>Thanks Dan!
>
>The ArchSupportMCJIT() functions in
>unittests/ExecutionEngine/MCJIT/MCJITTestBase.h uses "Host Triple" to
>check
>for compatibility. Since we cross-compile on X86, "Host Triple" for us
>wi...