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...h, and the corresponding macro SKIP_UNSUPPORTED_PLATFORM that is used to 'decorate' the test cases. I'm not sure if there's anything like that in place for JIT, but it can probably be ported over unless someone has a concern with the overall approach. Dan From: Jyotsna Verma <jverma at codeaurora.org<mailto:jverma at codeaurora.org>> Date: Monday, 11 March, 2013 2:28 PM To: LLVM List <llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>> Subject: [LLVMdev] Disabling ExecutionEngine tests for Hexagon Hi There, We want to disable all ExecutionEngine JIT/M...

Hi There, We want to disable all ExecutionEngine JIT/MCJIT tests (llvm/unittests/ExecutionEngine) for Hexagon. I have been looking into the test framework but haven't quite figured out how to turn them off. We cross compile Hexagon on X86 and are not interested in JIT support. Thanks, Jyotsna -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux

...Forum. -----Original Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Tuesday, August 21, 2012 11:28 AM To: Jyotsna Verma Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] TableGen related question for the Hexagon backend On Aug 20, 2012, at 9:22 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > Jakob, > > One more question. You had suggested 'ValueCols' as of type > list<list<string> >. Does the TableGen know how to extract it? It > appears to me that we may have to add support for that. You just start from getValueAsL...

...pport to express relations between instruction Jyotsna, I hadn't been following this, so I apologize if this has already been provided, but can you give a quick example of how this functionality is used? Thanks in advance, Hal On Tue, 28 Aug 2012 13:01:17 -0500 "Jyotsna Verma" <jverma at codeaurora.org> wrote: > Hi Jakob, > > Here is the first draft of the patch to add TableGen backend support > for the instruction mapping tables. Please take a look and let me know > your suggestions. As of now, I create one mapping table per relation > which results in...

Jyotsna, I hadn't been following this, so I apologize if this has already been provided, but can you give a quick example of how this functionality is used? Thanks in advance, Hal On Tue, 28 Aug 2012 13:01:17 -0500 "Jyotsna Verma" <jverma at codeaurora.org> wrote: > Hi Jakob, > > Here is the first draft of the patch to add TableGen backend support > for the instruction mapping tables. Please take a look and let me > know your suggestions. As of now, I create one mapping table per > relation which results into...

...PPORTED_PLATFORM that is used to 'decorate' the test >cases. > >I'm not sure if there's anything like that in place for JIT, but it can probably be >ported over unless someone has a concern with the overall approach. > > >Dan > >From: Jyotsna Verma ><jverma at codeaurora.org<mailto:jverma at codeaurora.org>> >Date: Monday, 11 March, 2013 2:28 PM >To: LLVM List <llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>> >Subject: [LLVMdev] Disabling ExecutionEngine tests for Hexagon > >Hi There, > >We want to disab...

...sage----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Monday, August 20, 2012 3:42 PM To: Jyotsna Verma Cc: 'Tony Linthicum'; llvmdev at cs.uiuc.edu Subject: Re: TableGen related question for the Hexagon backend On Aug 20, 2012, at 1:32 PM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: > In the Hexagon backend, a predicated instruction can translate into > another form called 'predicate new'. So, in our example of 'ADD', we > can have another transformation like this - > > ADD--- ---> ADDtrue -----> ADDtru_new...

On Aug 20, 2012, at 9:22 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > Jakob, > > One more question. You had suggested 'ValueCols' as of type > list<list<string> >. Does the TableGen know how to extract it? It appears to > me that we may have to add support for that. You just start from getValueAsLis...

>Since MCJIT works on x86, please don't remove it from the supported >platforms list. One downside of using the macro trick is that the test names >are still printed even when they are disabled. It sounds like you need to >modify the macro to also check for the target triple as well... This was just a temporary change to see how it works. >There isn't anything in MCJIT as

On 2013-03-13 3:15 AM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: > >I noticed "TARGET_HAS_JIT" flag in Makefile.config. Can I use this flag to >exclude MCJIT and JIT tests when not set? This will be a simpler change >than >modifying the macro. > >Thanks, >Jyotsna TARGET_HAS_JIT seems to be an auto...

...sage----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Monday, August 20, 2012 3:42 PM To: Jyotsna Verma Cc: 'Tony Linthicum'; llvmdev at cs.uiuc.edu Subject: Re: TableGen related question for the Hexagon backend On Aug 20, 2012, at 1:32 PM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: > In the Hexagon backend, a predicated instruction can translate into > another form called 'predicate new'. So, in our example of 'ADD', we > can have another transformation like this - > > ADD--- ---> ADDtrue -----> ADDtru_new...

On Aug 20, 2012, at 1:32 PM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: > In the Hexagon backend, a predicated instruction can translate into another > form called 'predicate new'. So, in our example of 'ADD', we can have > another transformation like this - > > ADD--- ---> ADDtrue -----> ADDtru_new...

...Forum. -----Original Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Tuesday, August 21, 2012 11:28 AM To: Jyotsna Verma Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] TableGen related question for the Hexagon backend On Aug 20, 2012, at 9:22 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > Jakob, > > One more question. You had suggested 'ValueCols' as of type > list<list<string> >. Does the TableGen know how to extract it? It > appears to me that we may have to add support for that. You just start from getValueAsL...

Hi Jacob, Your suggestion worked for the simple relations between instructions as you've included in your example. With one small change, I am able to represent more complex relations as well. In the Hexagon backend, a predicated instruction can translate into another form called 'predicate new'. So, in our example of 'ADD', we can have another transformation like this -

On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > > Currently, we rely on switch tables to transform between formats. However, > we would like to have a different mechanism to represent these relationships > instead of switch tables. I am thinking of modeling these relations in > HexagonInstrInfo.td f...

...riginal Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Thursday, August 02, 2012 5:24 PM To: Jyotsna Verma Cc: 'Tony Linthicum'; llvmdev at cs.uiuc.edu Subject: Re: TableGen related question for the Hexagon backend On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > > Currently, we rely on switch tables to transform between formats. > However, we would like to have a different mechanism to represent > these relationships instead of switch tables. I am thinking of > modeling these relations in HexagonInstrInfo.t...

On 2013-03-12 1:28 AM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: >Thanks Dan! > >The ArchSupportMCJIT() functions in >unittests/ExecutionEngine/MCJIT/MCJITTestBase.h uses "Host Triple" to >check >for compatibility. Since we cross-compile on X86, "Host Triple" for us >will >be "X86&quo...

...ng llvm. >Full details are available at: > http://lab.llvm.org:8011/builders/llvm-ppc64-linux1/builds/5382 > >Buildbot URL: http://lab.llvm.org:8011/ > >Buildslave for this Build: chinook > >Build Reason: scheduler >Build Source Stamp: [branch trunk] 180953 >Blamelist: jverma > >BUILD FAILED: failed test-llvm > >sincerely, > -The Buildbot > >

Hi, I'm looking for some suggestions on a problem related to the Hexagon backend. Hexagon architecture allows instructions in various formats. For example, we have 3 variations of the add instruction as defined below: ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 = add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is true ADDrr_np :

On Aug 16, 2012, at 1:39 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > Hi Everyone, > > After some more thoughts to the Jacob's suggestion of using multiclasses for > Opcode mapping, this is what I have come up with. Please take a look at the > design below and let me know if you have any suggestions/questions. Hi J...