Displaying 2 results from an estimated 2 matches for "just_a1".
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just_a0
2012 May 09
0
[LLVMdev] instructions requiring specific physical registers for operands
Jim,
> The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs:
> def myInst : baseclass<…, (outs GPRr2:$dst), (ins GPRr0:$src1, GPRr1:$src2), …>
> Use those reg classes in pattern to match also, and things should just work. The register allocator can take care of any reg-to-reg copies that are required.
As
2012 May 09
2
[LLVMdev] instructions requiring specific physical registers for operands
On May 9, 2012, at 4:27 AM, Anton Korobeynikov wrote:
> Hello Jonas,
>
>> I wonder, what would be the best solution for instructions that require
>> operands in a particular register, and even gives the result in a particular
>> register?
> You need to custom select such instruction. See e.g. div / idiv on x86
> as an example.
That's often easiest, yes;