search for: june2015

On 27 November 2016 at 16:51, Amara Emerson <amara.emerson at gmail.com> wrote: > There is nothing to stop other targets from using > stepvector/seriesvector. In fact for wide vector targets, often the IR > constant for representing a step vector is explicitly expressed as > <i32 0, i32 1, i32 2..> and so on (this gets really cumbersome when > your vector length is

...e: > The RISC-V vector proposal is still in the development stage, but it > will inevitably be vector length agnostic much like Hwacha. Krste gave > a talk about his proposal for the 'V' extension last year > <https://riscv.org/wp-content/uploads/2015/06/riscv-vector-workshop-june2015.pdf> > and I'm looking forward to his update at the RISC-V Workshop this > Wednesday, not least because I'm hoping he'll have done my homework > for me and contrast his proposal to what is publicly known about SVE. Thanks! This is really helpful! > The proposal include...

I have posted a patch that switches the API to one that supports this (yet non-existent functionality) earlier: https://reviews.llvm.org/D24631 The comments from that were incorporated into the following RFC. Motivation: Certain targets feature "variable-sized" registers, i.e. a situation where the register size can be configured by a hardware switch. A common instruction set

Hi everyone, Since I haven't said anything on the mailing list before, a quick introduction. I'm an intern at Apple, and over the summer I implemented a prototype for an outlining pass for code size in LLVM. Now I'm seeking to eventually upstream it. I have the preliminary code on GitHub right now, but it's still very prototypical (see the code section).