Displaying 6 results from an estimated 6 matches for "jumptarget".
2009 Jun 03
5
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
...;
+
+ // table entries are 4 bytes, so multiple index by 4
+ const SDValue ScaledIndex = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
+
+ // add scaled index to table beginning
+ const SDValue TabEntryAddr = DAG.getNode(ISD::ADD, dl, PTy, ScaledIndex, Table);
+ const SDValue JumpTarget = DAG.getLoad(PTy, dl, Chain, TabEntryAddr, NULL, 0);
+
+ return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, JumpTarget, JTI, UId);
+}
+
+
+static SDValue LowerBR_JT_Inline(SDValue Op,
+ SelectionDAG &DAG,
+ bool isPIC,
+...
2009 Jun 11
0
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
On Jun 8, 2009, at 2:42 PM, robert muth wrote:
> On Sun, Jun 7, 2009 at 11:53 PM, Evan Cheng <evan.cheng at apple.com>
> wrote:
>>
>> On Jun 7, 2009, at 6:59 AM, robert muth wrote:
>>
>>> On Sat, Jun 6, 2009 at 4:51 PM, Evan Cheng<evan.cheng at apple.com>
>>> wrote:
>>>> +cl::opt<std::string>
2009 Jun 08
2
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
On Sun, Jun 7, 2009 at 11:53 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>
> On Jun 7, 2009, at 6:59 AM, robert muth wrote:
>
>> On Sat, Jun 6, 2009 at 4:51 PM, Evan Cheng<evan.cheng at apple.com>
>> wrote:
>>> +cl::opt<std::string> FlagJumpTableSection("jumptable-section",
>>> +
2009 Jun 24
2
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
...;
+
+ // table entries are 4 bytes, so multiple index by 4
+ const SDValue ScaledIndex = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
+
+ // add scaled index to table beginning
+ const SDValue TabEntryAddr = DAG.getNode(ISD::ADD, dl, PTy, ScaledIndex, Table);
+ const SDValue JumpTarget = DAG.getLoad(PTy, dl, Chain, TabEntryAddr, NULL, 0);
+
+ return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, JumpTarget, JTI, UId);
+}
+
+
+static SDValue LowerBR_JT_Inline(SDValue Op,
+ SelectionDAG &DAG,
+ bool isPIC,
+...
2015 Jan 11
3
[LLVMdev] [RFC] [PATCH] add tail call optimization to thumb1-only targets
...o *RegInfo =
+ static_cast<const Thumb1RegisterInfo *>
+ (MF.getSubtarget().getRegisterInfo());
+
+ // Re-adjust stack pointer for LR content still residing on the stack.
+ emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, 4);
+ }
+
+ MachineOperand &JumpTarget = MBBI->getOperand(0);
+
+ assert (MBBI->getOpcode() == ARM::TCRETURNri);
+ DebugLoc dl = MBBI->getDebugLoc();
+
+ BuildMI(MBB, MBBI, dl,
+ TII.get(ARM::tTAILJMPr))
+ .addReg(JumpTarget.getReg(), RegState::Kill);
+
+ MachineInstr *NewMI = std::prev(MBBI);
+ fo...
2015 May 18
2
[LLVMdev] RFC: New EH representation for MSVC compatibility
On Sat, May 16, 2015 at 7:29 AM, Steve Cheng <steve.ckp at gmail.com> wrote:
> On 2015-05-15 18:37:58 -0400, Reid Kleckner said:
>
> After a long tale of sorrow and woe, my colleagues and I stand here
>> before you defeated. The Itanium EH representation is not amenable to
>> implementing MSVC-compatible exceptions. We need a new representation that
>> preserves