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Hi, I'm doing a backend port and I'm having trouble with adds that have negative immediates. My architecture only has instructions for subtracting and adding 8bit immediate values (they will be zero-extended, thus unsigned). Bigger immediates have to be moved in a register first. The problem is: Expressions like "b - 1" result in "add nsw i32 %b, -1" in LLVM IR. They

> Hey, > > I have an odd problem with printing prefixed global symbols in my > AsmPrinter. > > In my MCAsmInfo subclass implementation, I set > > GlobalPrefix = "%"; > > > because my assembler needs this to avoid name collisions. > Now, whenever a global symbol (be it a label, mbb operand ,etc.) gets > printed, it is encapsulated in quotes.

On 04/14/2013 02:17 PM, Dong Chen wrote: > hello guys: > i am thinking about what kind of C instructions can turn into llvm IR > 'select' instruction. > i tried "d=a?b:c" and compiled it using clang, i still didn't get 'select' > is there anybody who knows this? > thank you Did you try to compile this with optimization enabled? (at least -O1) For

Hi, is there any documentation on which functions clang assumes to be provided by a freestanding environment? Are that really only memcpy, memmove, memset and memcmp? Greetings, Jan

Hey, I have an odd problem with printing prefixed global symbols in my AsmPrinter. In my MCAsmInfo subclass implementation, I set GlobalPrefix = "%"; because my assembler needs this to avoid name collisions. Now, whenever a global symbol (be it a label, mbb operand ,etc.) gets printed, it is encapsulated in quotes. With other chars than '%' everything is okay... I also

Hi there, I'm having a hard time with promoting operands from i1 to i32 in my backend... I have to register classes, VTs are i1 and i32. The i1 registers are only for predication and conditional jumps, so I want to use them with brcond, setcc. There are no instructions to directly load a value in an i1 register or to copy between i1 and i32, so I need the DAG Legalizing Pass to not generate

Hi there, I am currently trying to create an LLVM Backend for a RISC architecture and running into problems with setCC and brcond. First a few explanations: The architecture doesn't have a dedicated flag register, but seven 1-bit-wide so called "condition registers", c0-c6, which can be set by e.g. a compare instruction: > cmp ne, c0, r1, 123 It also supports conditional