Displaying 2 results from an estimated 2 matches for "jrinst".
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brinst
2012 Aug 07
0
[LLVMdev] [RFC] Hexagon insn table refactoring
...efactoring of the current insn tables will be necessary.
I intend to create classes for each insn with the opcode and have the
current insn definitions use the current names but based on a insn class.
For example, a conditional indirect branch insn is currently defined as:
def JMPR_cdnNotPt_V3: JRInst<(outs),
(ins PredRegs:$src1, IntRegs:$src2),
"if (!$src1.new) jumpr:t $src2",
[]>,
Requires<[HasV3T]>;
Its new definition would be like this:
let Defs = [PC], isP...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...10 +41,11 @@ let isCall = 1, neverHasSideEffects = 1,
>> }
>>
>>
>> +// Jump to address from register
>> // if(p?.new) jumpr:t r?
>> let isReturn = 1, isTerminator = 1, isBarrier = 1,
>> Defs = [PC], Uses = [R31] in {
>> - def JMPR_cPnewt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
>> + def JMPR_cdnPt_V3: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
>> "if ($src1.new) jumpr:t $src2",
>> []>, Requires<[HasV3T]>;
>> }
>>...