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> On Jul 19, 2016, at 12:57 PM, Pete Cooper via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Renato >> On Jul 19, 2016, at 9:42 AM, Renato Golin via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> A few basic rules to get accepted are if: >> * the target exists and can be easily purchased / emulated

The ISA & encoding is documented in the comments and diagrams of lib/Target/Lanai/LanaiInstrFormats.td. If that makes sense I'll add a link to this tablegen in docs/CompilerWriterInfo.rst. Thanks, Jacques On Tue, Feb 9, 2016 at 2:12 PM, Sean Silva <chisophugis at gmail.com> wrote: > Do you have a psABI document? Or an ISA reference? Or an encoding > reference? > > I

Do you MC support? Cheers, Rafael On Feb 9, 2016 1:12 PM, "Jacques Pienaar via llvm-dev" < llvm-dev at lists.llvm.org> wrote: > > > On Tue, Feb 9, 2016 at 10:05 AM, Chandler Carruth <chandlerc at google.com> > wrote: > >> On Tue, Feb 9, 2016 at 9:58 AM Hal Finkel via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >>>

On Tue, Feb 9, 2016 at 9:58 AM Hal Finkel via llvm-dev < llvm-dev at lists.llvm.org> wrote: > ----- Original Message ----- > > From: "Jacques Pienaar via llvm-dev" <llvm-dev at lists.llvm.org> > > To: llvm-dev at lists.llvm.org > > Sent: Tuesday, February 9, 2016 11:40:21 AM > > Subject: [llvm-dev] [RFC] Lanai backend > > > Hi all, >

Hi all, We would like to contribute a new backend for the Lanai processor (derived from the processor described in [1]). Lanai is a simple in-order 32-bit processor with: * 32 32-bit registers, including: * 2 registers with fixed values; * 4 used for program state tracking (PC, SP, FP, RCA); * 2 reserved for explicit usage by user (R10 and R11), used in threading library; * Up