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----- Original Message ----- > From: "Bruce Hoult" <bruce at hoult.org> > To: "Johnny Val" <johnnydval at gmail.com> > Cc: "<llvmdev at cs.uiuc.edu>" <llvmdev at cs.uiuc.edu> > Sent: Thursday, October 23, 2014 8:31:35 AM > Subject: Re: [LLVMdev] Question regarding getElementPtr/Addressing modes in backend > > Many CPU instruction sets have "autoincreme...

...tion does not interfere in the generated assembly code. I'll check the file that describes the registers and I hope understand why the assembly code is printed wrong (now is printed things like add r1, r0, -40). Cheers, Carlos Carlos Almeida Jr On Thu, Nov 27, 2014 at 7:56 AM, Johnny Val <johnnydval at gmail.com> wrote: > Hi Carlos, > > LLVM will do this automatically for you! There is no need for a pseudo > instruction in this case. As long as you have a way of adding two i32s (or > any other type) using registers then LLVM will automatically do what you > described wh...

...the offset > MClass. See SparcInstrInfo.td (and probably others) for examples. > > I'm assuming you meant r1 = *(i0 + m0) rather than r1 = *(i0 += m0)? I > don't know how you'd achieve that latter. > > Steve Montgomery > > On 21 Oct 2014, at 17:15, Johnny Val <johnnydval at gmail.com> wrote: > > > Hi, > > > > I am writing a backend and having issues with properly lowering the > result of getElementPtr ( specifically the add node that it generates). > > > > If we take this IR: > > > > %struct.rectangle = type { i2...

...since lldb has just assumes that the size of a byte is universally 8-bits. At some stage, I *think* at some stage we'd like to derive a compiler, from the "same code-base" (i.e. llvm) and I wondered how tricky this would be. Matt On Tue, 9 Sep 2014 11:49:01 +0100 Johnny Val <johnnydval at gmail.com> wrote: > Hi Matthew, > > The byte==8 bits is more of a Clang issue rather than an LLVM issue. I > believe your bigger issue will be the fact that you would need to make > i24's a legal type in your backend, which as far as I know (unless > something has ch...

Hi, I am writing a backend and having issues with properly lowering the result of getElementPtr ( specifically the add node that it generates). If we take this IR: %struct.rectangle = type { i24, i24 } ; Function Attrs: nounwind readonly define i24 @area(%struct.rectangle* nocapture readonly %r) #0 { entry: %width = getelementptr inbounds %struct.rectangle* %r, i16 0, i32 0 %0 = load i24*

...ze of a byte is > universally 8-bits. At some stage, I *think* at some stage we'd like to > derive a compiler, from the "same code-base" (i.e. llvm) and I > wondered how tricky this would be. > > Matt > > On Tue, 9 Sep 2014 11:49:01 +0100 > Johnny Val <johnnydval at gmail.com> wrote: > > > Hi Matthew, > > > > The byte==8 bits is more of a Clang issue rather than an LLVM issue. I > > believe your bigger issue will be the fact that you would need to make > > i24's a legal type in your backend, which as far as I know...

Hi, I'm a beginner user using LLVM, and I'm trying to create a new backend using CPU0 Tutorial as reference. I have two instructions for add: add and addi (this is a pseudo instruction, but imediate operations is not available in architecture). That is my idea: When the LLVM instruction selection find addi r3 = r2 + value must convert to this: - load r1, value - add r3 = r2 + r1 In

Hi, We have some DSP architectures (kalimba) which have 24-bits as their "minimum addressable unit". So this means that the sizeof a char (and an int and a short for that matter) is 24-bits. I quickly read the posted link WritingAnLLVMBackend.html but did not see an obvious answer to the following question: Is it possible to write a backend that faithfully represents these

Hi, I am working on a new back-end for LLVM. This architecture has two register types, data(A) and accumulator(B). A registers are i32 where as B registers are i64. This is causing me some headaches, as far as I can tell, it's not really possible to mix the two using tablegen? In the hardware, every instruction can either take an A register or a B register, in tablegen (as far as I can