search for: jne_1

Displaying 5 results from an estimated 5 matches for "jne_1".

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2012 Dec 05
2
[LLVMdev] questions about the mc-relax-all flag
...t? As it stands now, the flag sounds like a binary predicate - either relax all, or don't relax all. Maybe something like "mc-early-relaxation" would be more descriptive? Thanks in advance for any insights, Eli (*) For instance in the case of X86, the MCInst emitter shrinks JNE_4 to JNE_1 counting on relaxation in the assembler to fix it if needed.
2012 Dec 06
0
[LLVMdev] questions about the mc-relax-all flag
...s like a binary predicate - either relax all, or don't relax all. > Maybe something like "mc-early-relaxation" would be more descriptive? > > Thanks in advance for any insights, > Eli > > (*) For instance in the case of X86, the MCInst emitter shrinks JNE_4 > to JNE_1 counting on relaxation in the assembler to fix it if needed. > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
...;                                                   . > >                                                   . > >                                                   . > > TEST32rr %ESI<kill>, %R8D<kill>, %EFLAGS<imp-def>; dbg:FastBoard.cpp:1940:10 > > JNE_1 <BB#1>, %EFLAGS<imp-use,kill>; dbg:FastBoard.cpp:1940:9 > > BB#1: > > %CL<def> = COPY %R9B<kill>, %ECX<imp-use,kill>, %ECX<imp-def>; > dbg:FastBoard.cpp:1938:38 > >                                                    . > >        ...
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
...gt;> . >>> >>> . >>> >>> TEST32rr %ESI<kill>, %R8D<kill>, %EFLAGS<imp-def>; >>> dbg:FastBoard.cpp:1940:10 >>> >>> JNE_1 <BB#1>, %EFLAGS<imp-use,kill>; dbg:FastBoard.cpp:1940:9 >>> >>> BB#1: >>> >>> %CL<def> = COPY %R9B<kill>, %ECX<imp-use,kill>, %ECX<imp-def>; >>> dbg:FastBoard.cpp:1938:38 >>> >>>...
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
Hi Geoff/Krzyssztof, Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts. Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a