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2014 Nov 13
2
[LLVMdev] [RFC] TableGen help for relaxation
...the x86 relaxation code with
a comment wondering if TableGen could improve life.
Does the following outline sound interesting?
1) Add a new field of type 'Instruction' to the Instruction class
called "RelaxedInstr"
2) Target instructions optionally set RelaxedInstr, as in:
def JMP32 : Instruction<stuff>; // no relaxation from here
def JMP8 : Instruction<stuff> {
let RelaxedInstr = JMP32; // relax to 32-bit jmp
}
3) The tblgen -gen-instr-info processor uses RelaxedInstruction to
create the RelaxedOpcode field for the corresponding MCInst. The
RelaxedOpcode...