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...PLT flags with MachineInstrBuilder in FastISel pass (without failing back to DAG lowering). The new patch is attached, and the test case is not changed. Sorry for your inconvenience. Please have a look. Thanks for your help. Sincerely, Logan On Wed, Aug 21, 2013 at 10:52 PM, JF Bastien <jfb at google.com> wrote: > lgtm > > > On Wed, Aug 21, 2013 at 3:18 AM, Anton Korobeynikov < > anton at korobeynikov.info> wrote: > >> LGTM >> >> On Wed, Aug 21, 2013 at 1:51 PM, Logan Chien <tzuhsiang.chien at gmail.com> >> wrote: >> >...

On Thu, Jan 14, 2016 at 1:35 PM, David Majnemer <david.majnemer at gmail.com> wrote: > > > On Thu, Jan 14, 2016 at 1:13 PM, JF Bastien <jfb at google.com> wrote: > >> On Thu, Jan 14, 2016 at 1:10 PM, David Majnemer via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >>> >>> >>> On Wed, Jan 13, 2016 at 7:00 PM, Hans Boehm via llvm-dev < >>> llvm-dev at lists.llvm.o...

...tISel pass (without failing back to DAG lowering). > > The new patch is attached, and the test case is not changed. Sorry for > your inconvenience. Please have a look. Thanks for your help. > > Sincerely, > Logan > > > On Wed, Aug 21, 2013 at 10:52 PM, JF Bastien <jfb at google.com> wrote: > >> lgtm >> >> >> On Wed, Aug 21, 2013 at 3:18 AM, Anton Korobeynikov < >> anton at korobeynikov.info> wrote: >> >>> LGTM >>> >>> On Wed, Aug 21, 2013 at 1:51 PM, Logan Chien <tzuhsiang.chien at gma...

..._PLT flags with MachineInstrBuilder in FastISel pass (without failing back to DAG lowering). The new patch is attached, and the test case is not changed. Sorry for your inconvenience. Please have a look. Thanks for your help. Sincerely, Logan On Wed, Aug 21, 2013 at 10:52 PM, JF Bastien <jfb at google.com<mailto:jfb at google.com>> wrote: lgtm On Wed, Aug 21, 2013 at 3:18 AM, Anton Korobeynikov <anton at korobeynikov.info<mailto:anton at korobeynikov.info>> wrote: LGTM On Wed, Aug 21, 2013 at 1:51 PM, Logan Chien <tzuhsiang.chien at gmail.com<mailto:tzuhsia...

On 01/14/2016 04:05 PM, Hans Boehm via llvm-dev wrote: > > > On Thu, Jan 14, 2016 at 1:37 PM, JF Bastien <jfb at google.com > <mailto:jfb at google.com>> wrote: > > On Thu, Jan 14, 2016 at 1:35 PM, David Majnemer > <david.majnemer at gmail.com <mailto:david.majnemer at gmail.com>> wrote: > > > > On Thu, Jan 14, 2016 at 1:13 PM, JF Bastien <jf...

...son Novathor with > > Linaro, code works. It also works when I use LLVM to generate fma > > (using llc -mtriple=armv7-eabi). Maybe someone from ARM can answer > the question ? > > > > > > > > Seb > > > > > > > > From: JF Bastien [mailto:jfb at google.com] > > Sent: Friday, November 09, 2012 5:36 PM > > To: Sebastien DELDON-GNB > > Cc: Anitha Boyapati; llvmdev at cs.uiuc.edu > > > > > > Subject: Re: [LLVMdev] fmac generation for cortex-a9 > > > > > > > > AFAIK A9 doesn't h...

...also works when I use LLVM to generate fma > > > (using llc -mtriple=armv7-eabi). Maybe someone from ARM can answer > > the question ? > > > > > > > > > > > > Seb > > > > > > > > > > > > From: JF Bastien [mailto:jfb at google.com] > > > Sent: Friday, November 09, 2012 5:36 PM > > > To: Sebastien DELDON-GNB > > > Cc: Anitha Boyapati; llvmdev at cs.uiuc.edu > > > > > > > > > Subject: Re: [LLVMdev] fmac generation for cortex-a9 > > > > > > &g...

...point MAC not for fused MAC. Than I realized that we spoke about fma instead of fmac. So back to the original problem why when using -mcpu=cortex-a9 VMLA/VMLS are not generated and when I use -mtriple=armv7-eabi they are ? Best Regards Seb ________________________________________ De : JF Bastien [jfb at google.com] Date d'envoi : vendredi 9 novembre 2012 18:45 À : Sebastien DELDON-GNB Cc : Renato Golin; llvmdev at cs.uiuc.edu Objet : Re: [LLVMdev] fmac generation for cortex-a9 cat /proc/cpuinfo ? Are you sure it's generating VFMA and not VMLA? On Fri, Nov 9, 2012 at 9:35 AM, Sebasti...

On Mon, Mar 31, 2014 at 1:01 PM, Renato Golin <renato.golin at linaro.org>wrote: > On 31 March 2014 20:55, Tim Northover <t.p.northover at gmail.com> wrote: > > I'd almost prefer to leave it in for the bugs to be discovered > > (perhaps after some simple tests of our own). ARM went wirthout > > FastISel support on Linux for years simply because it was declared

...; > Sent: Tuesday, August 20, 2013 9:47 PM >> > To: Gordon Keiser >> > Cc: llvmdev at cs.uiuc.edu; JF Bastien >> > Subject: Re: [LLVMdev] Broken PLT on ARM from R183966 >> > >> > Filing a bug would be a good start, go ahead and cc me and >> > jfb at google.com. >> > >> > Thanks! >> > >> > -eric >> > >> > On Tue, Aug 20, 2013 at 6:10 PM, Gordon Keiser <gkeiser at arxan.com> >> > wrote: >> > > For ARM targets on linux, revision 183966 made Fast ISel default. >...

Replied too early... Below: On Tue, May 10, 2016 at 2:04 PM, JF Bastien <jfb at google.com> wrote: > Thanks for the writeup, that is indeed pretty ugly. Simple > asm(:::"memory") isn't sufficient either, since the regalloc can decode to > spill :-( > > On Tue, May 10, 2016 at 12:22 PM, James Knight via llvm-dev < > llvm-dev at lists.ll...

> > This seems interesting, I have a few questions: > > > Has the ISA been finalized yet or is it still a work in progress? Will > there be a fixed number of registers? > The design document has a high-level idea of the ISA, or rather of the AST we're thinking of going with: https://github.com/WebAssembly/design/blob/master/AstSemantics.md The final encoding isn't

On 14 March 2014 16:34, JF Bastien <jfb at google.com> wrote: > How does this overlap with: > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140310/thread.html#208333 The builtin was created to call __clear_cache() on platforms that need it (like ARM and MIPS), but to be ignored on others (like x86_64). Thi...

> > > A primary drawback in the above patch is the static use of Cache Line > Size. I wish to get this data from tblgen/TTI and I am happy to submit > patches on it. > > Yes, this sounds like the right direction. The targets obviously need to > provide this information. > I'd like to help review this as it'll be necessary to implement http://wg21.link/p0154r1

...0, 2013 9:47 PM > >> > To: Gordon Keiser > >> > Cc: llvmdev at cs.uiuc.edu; JF Bastien > >> > Subject: Re: [LLVMdev] Broken PLT on ARM from R183966 > >> > > >> > Filing a bug would be a good start, go ahead and cc me and > >> > jfb at google.com. > >> > > >> > Thanks! > >> > > >> > -eric > >> > > >> > On Tue, Aug 20, 2013 at 6:10 PM, Gordon Keiser <gkeiser at arxan.com> > >> > wrote: > >> > > For ARM targets on linux, revi...

...> From: Eric Christopher [mailto:echristo at gmail.com] > Sent: Tuesday, August 20, 2013 9:47 PM > To: Gordon Keiser > Cc: llvmdev at cs.uiuc.edu; JF Bastien > Subject: Re: [LLVMdev] Broken PLT on ARM from R183966 > > Filing a bug would be a good start, go ahead and cc me and jfb at google.com. > > Thanks! > > -eric > > On Tue, Aug 20, 2013 at 6:10 PM, Gordon Keiser <gkeiser at arxan.com> > wrote: > > For ARM targets on linux, revision 183966 made Fast ISel default. > > Unfortunately, Fast ISel is broken in terms of applying the &gt...

Filing a bug would be a good start, go ahead and cc me and jfb at google.com. Thanks! -eric On Tue, Aug 20, 2013 at 6:10 PM, Gordon Keiser <gkeiser at arxan.com> wrote: > For ARM targets on linux, revision 183966 made Fast ISel default. > Unfortunately, Fast ISel is broken in terms of applying the ARMII::MO_PLT > flags to calls in PIC mode (a...

On Fri, Sep 25, 2015 at 2:17 PM, JF Bastien <jfb at google.com> wrote: > Looks like this was caused by r248294. Author CC'ed. > > On Fri, Sep 25, 2015 at 1:46 PM, Richard Pennington via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> >> Hi, >> >> I was compiling libc++ with a recent TOT (248571)...

Hi Bastien, Weird gcc is generating fma for my platform STEricsson Novathor with Linaro, code works. It also works when I use LLVM to generate fma (using llc -mtriple=armv7-eabi). Maybe someone from ARM can answer the question ? Seb From: JF Bastien [mailto:jfb at google.com] Sent: Friday, November 09, 2012 5:36 PM To: Sebastien DELDON-GNB Cc: Anitha Boyapati; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] fmac generation for cortex-a9 AFAIK A9 doesn't have VFPv4 or AdvSIMDv2, so it doesn't have VFMA. I don't know what LLVM does, but it should...

For ARM targets on linux, revision 183966 made Fast ISel default. Unfortunately, Fast ISel is broken in terms of applying the ARMII::MO_PLT flags to calls in PIC mode (at least when emitting assembly); it never does this. The normal ISel pass handles this situation correctly so a temporary local change to disable FastISel for linux / NaCl targets is working for me right now. I'm not very