search for: jemmapes

Displaying 19 results from an estimated 19 matches for "jemmapes".

2012 Mar 26
2
[LLVMdev] PBQP & CalcSpillWeights
...ts, and do not appear here, being handled by the PBQPBuilder default base class. A few instructions have 1 or 2 pairs of registers, and are all handled by the 2 passes above. Thanks for your help, -- Arnaud de Grandmaison Senior CPU engineer Business Unit Digital Tuner Parrot S.A. 174, quai de Jemmapes 75010 Paris - France Phone: +33 1 48 03 84 59 -------------- next part -------------- A non-text attachment was scrubbed... Name: FemtoRegisterAllocator.cpp Type: text/x-c++src Size: 17631 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120326/07c07e0e/atta...
2012 Mar 27
0
[LLVMdev] PBQP & CalcSpillWeights
...the PBQPBuilder default base class. A few instructions have 1 or 2 > pairs of registers, and are all handled by the 2 passes above. > > Thanks for your help, > -- > Arnaud de Grandmaison > Senior CPU engineer > Business Unit Digital Tuner > > Parrot S.A. > 174, quai de Jemmapes > 75010 Paris - France > Phone: +33 1 48 03 84 59
2012 Mar 27
2
[LLVMdev] PBQP & CalcSpillWeights
...t; have 1 or 2 pairs of registers, and are all handled by the 2 passes > > above. > > > > Thanks for your help, > > -- > > Arnaud de Grandmaison > > Senior CPU engineer > > Business Unit Digital Tuner > > > > Parrot S.A. > > 174, quai de Jemmapes > > 75010 Paris - France > > Phone: +33 1 48 03 84 59 -------------- next part -------------- A non-text attachment was scrubbed... Name: invalid-spill.tar.gz Type: application/x-compressed-tar Size: 6984 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attach...
2012 Apr 19
1
[LLVMdev] PBQP & CalcSpillWeights
...gt; > >>>> Thanks for your help, > >>>> -- > >>>> Arnaud de Grandmaison > >>>> Senior CPU engineer > >>>> Business Unit Digital Tuner > >>>> > >>>> Parrot S.A. > >>>> 174, quai de Jemmapes > >>>> 75010 Paris - France > >>>> Phone: +33 1 48 03 84 59<tel:%2B33%201%2048%2003%2084%2059> > > _______________________________________________ > > LLVM Developers mailing list > > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > &...
2012 Apr 05
2
[LLVMdev] PBQP & CalcSpillWeights
...dled by the 2 passes > > > above. > > > > > > Thanks for your help, > > > -- > > > Arnaud de Grandmaison > > > Senior CPU engineer > > > Business Unit Digital Tuner > > > > > > Parrot S.A. > > > 174, quai de Jemmapes > > > 75010 Paris - France > > > Phone: +33 1 48 03 84 59<tel:%2B33%201%2048%2003%2084%2059>
2012 Apr 03
0
[LLVMdev] PBQP & CalcSpillWeights
...andled by the 2 passes > > > above. > > > > > > Thanks for your help, > > > -- > > > Arnaud de Grandmaison > > > Senior CPU engineer > > > Business Unit Digital Tuner > > > > > > Parrot S.A. > > > 174, quai de Jemmapes > > > 75010 Paris - France > > > Phone: +33 1 48 03 84 59 > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120403/8619d4c5/attachment.html>
2013 May 17
1
Opus ARM optimizations
Hello, I've been working on optimizations for ARMv5E architecture and Cortex-A8 for both decoder and encoder and my company is agree to contribute to upstream. Could you tell me how to do it ? Best regards, -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France
2013 May 27
0
[Patch] Check if opus_compare is executable in run_vectors.sh
If opus_compare doesn't exist or isn't executable, tests failed normally which could be misleading. So test for existence and mode to avoid this ambiguity. -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Check-if-opus_compare-is-executable-in-run_vectors.s.patch Type: text/x-patch Size: 0 bytes Desc: not available Url : http://lists.xiph.org/pipermail/opus/attachments/20130527/3177ffc6/attach...
2013 Jun 11
0
Bug fix in celt_lpc.c and some xcorr_kernel, optimizations
...version to avoid read past "y" buffer and fix > register garbage when it's inlined. > > Best regards, > > P.S: I made a mistake so some of my e-mails have not been sent to this > mailing list. I apologize for this. > > -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France
2012 Apr 11
0
[LLVMdev] PBQP & CalcSpillWeights
...es >>>> above. >>>> >>>> Thanks for your help, >>>> -- >>>> Arnaud de Grandmaison >>>> Senior CPU engineer >>>> Business Unit Digital Tuner >>>> >>>> Parrot S.A. >>>> 174, quai de Jemmapes >>>> 75010 Paris - France >>>> Phone: +33 1 48 03 84 59<tel:%2B33%201%2048%2003%2084%2059> > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/m...
2012 Mar 23
0
[LLVMdev] PBQP & CalcSpillWeights
Hi Arnaud, LiveInterval::markNotSpillable() sets the live interval's spill weight to infinity. For well-formed PBQP graphs (i.e. ones that have some finite-cost solution), PBQP should never chose to spill such an interval. The two possibilities for this crash are that the input graph has no finite-cost solution, or that you've exposed a bug in the PBQP solver. >From memory your target
2013 Jun 07
1
Bug fix in celt_lpc.c and some xcorr_kernel optimizations
Unfortunately I don't have a setup that lets me easily profile ARM code, so I really can't tell which method is faster (though I suspect Mr. Zanelli's code is). Let me offer up another intrinsic version of the NEON xcorr_kernel that is almost identical to the SSE version, and more in line with Mr. Zanelli's code: static inline void xcorr_kernel_neon(const opus_val16 *x, const
2012 Mar 21
2
[LLVMdev] PBQP & CalcSpillWeights
Hi All, I finally had a chance to get back to my pbqp trials, now using the 3.0 release. I still hit the same assert : "Attempting to spill already spilled value." This is triggered because in RegAllocPBQP::mapPBQPToRegAlloc, a vreg node is either : - a physical register (problem.isPRegOption(vreg, alloc)), - or a spill (problem.isSpillOption(vreg, alloc)) The problem is that pass
2013 Jan 18
2
[LLVMdev] Weird volatile propagation ?
Hi All, Using clang+llvm at head, I noticed a weird behaviour with the following reduced testcase : $ cat test.c #include <stdint.h> struct R { uint16_t a; uint16_t b; }; volatile struct R * const addr = (volatile struct R *) 416; void test(uint16_t a) { struct R r = { a, 1 }; *addr = r; } $ clang -O2 -o - -emit-llvm -S -c test.c ; ModuleID = 'test.c' target
2013 Jan 20
0
[LLVMdev] codegen of volatile aggregate copies (was "Weird volatile propagation" on llvm-dev)
...store volatile i16 1, i16* inttoptr (i64 418 to i16*), align 2 > ret void > } > > Using LLVM-3.1, I get the expected code. Would this ring a bell to anybody ? > > Cheers, > -- Arnaud de Grandmaison Senior CPU engineer Business Unit Digital Tuner Parrot S.A. 174, quai de Jemmapes 75010 Paris - France Phone: +33 1 48 03 84 59
2013 May 17
1
[Patch]01-Add ARM5E macros
Hello, This is a first patch which add macros for ARMv5E. Also, I copy headers from other files and add company name, tell me if I'm wrong. Also, if you have any question or comment about it, feel free to contact me. Best regards, -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France -------------- next part -------------- diff --git a/celt/fixed_arm5e.h b/celt/fixed_arm5e.h new file mode 100644 index 0000000..9eb970a --- /dev/null +++ b/celt/fixed_arm5e.h @@ -0,0 +1,99 @@ +/* Copyright (C) 2007-2009 Xiph.Org Foundation + Copyright (C) 2003-2008 Jean-Marc V...
2013 May 21
0
[PATCH] 02-
...acros instead of (sum += a*b) and unroll a loop by 2. It increase performance when using optimized macros (ex: ARMv5E). A possible side effect of loop unroll is that i don't check for odd length here. - Add NEON version of FIR filter and autocorr -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France -------------- next part -------------- diff --git a/celt/celt_lpc.c b/celt/celt_lpc.c index d2addbf..14a7839 100644 --- a/celt/celt_lpc.c +++ b/celt/celt_lpc.c @@ -33,6 +33,10 @@ #include "stack_alloc.h" #include "mathops.h" +#ifdef ARM_HAVE_NEON +#includ...
2013 May 21
2
[PATCH] 02-Add CELT filter optimizations
...rmance when using optimized macros (ex: ARMv5E). A possible side effect of loop unroll is that i don't check for odd length here. - Add NEON version of FIR filter and autocorr - Add a section in autoconf in order to check NEON support Best regards, -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France -------------- next part -------------- diff --git a/celt/celt_lpc.c b/celt/celt_lpc.c index d2addbf..14a7839 100644 --- a/celt/celt_lpc.c +++ b/celt/celt_lpc.c @@ -33,6 +33,10 @@ #include "stack_alloc.h" #include "mathops.h" +#ifdef ARM_HAVE_NEON +#includ...
2013 May 23
2
ASM runtime detection and optimizations
...design which had been discussed on IRC. Also, i notice a little drawback: we must propagate the arch index through functions which don't have codec state as argument. However, if it's look good, i will continue to implement it. Best regards, -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France -------------- next part -------------- diff --git a/Makefile.am b/Makefile.am index f04e3bc..06d4283 100644 --- a/Makefile.am +++ b/Makefile.am @@ -5,7 +5,7 @@ lib_LTLIBRARIES = libopus.la DIST_SUBDIRS = doc -INCLUDES = -I$(top_srcdir)/include -I$(top_srcdir)/celt -I$(top_s...