Displaying 8 results from an estimated 8 matches for "jeehoon".
2015 Feb 23
2
[LLVMdev] LLVM IR in DAG form
...use edges to help in analysing memory operations. I don't think
we've settled on a concrete proposal yet, but I wouldn't be surprised to
see something in the form of an analysis pass which produces 'def-use'
information for memory operations.
Philip
On 02/22/2015 07:47 PM, Jeehoon Kang wrote:
> Thank you David and Jeremy!
>
> I am quite convinced that LLVM IR in SSA form already expresses data
> dependence quite well, as said David and Jeremy. Expressing IR in DAG
> may enable more optimizations on memory operations, but the benefit
> seems to be not so...
2015 Feb 21
2
[LLVMdev] LLVM IR in DAG form
On Sat, Feb 21, 2015 at 6:38 PM, David Chisnall <David.Chisnall at cl.cam.ac.uk
> wrote:
>
> > On 21 Feb 2015, at 05:59, Jeehoon Kang <jeehoon.kang at sf.snu.ac.kr>
> wrote:
> >
> > this is Jeehoon Kang, a CS PhD student and a newbie to LLVM.
> >
> > I am wondering why LLVM IR's basic block consists of a list of
> instructions,
> > rather than a DAG of instruction as in the low l...
2015 Feb 21
2
[LLVMdev] LLVM IR in DAG form
Hi all,
this is Jeehoon Kang, a CS PhD student and a newbie to LLVM.
I am wondering why LLVM IR's basic block consists of a list of instructions,
rather than a DAG of instruction as in the low level (ISelectionDAG).
My gut feeling tells me that LLVM IR in DAG form may admit more
optimisations in a systematic manner....
2015 Jul 17
2
[LLVMdev] Suspicious behavior of mem2reg (promoteSingleBlockAlloca)
Hi LLVMDev,
this is Jeehoon Kang, a Ph.D. student of Software Foundations Laboratory (
http://sf.snu.ac.kr), Dept. of Computer Science & Engineering, Seoul
National University. Our group studied the mem2reg pass, and we got a
question on its algorithm.
As far as I understand, the mem2reg pass essentially uses the SSA
co...
2018 Apr 10
2
Miscompilation bugs in GVN.cpp and PromoteMemoryToRegister.cpp?
On Tue, Apr 10, 2018 at 10:28 AM, Friedman, Eli via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 4/9/2018 8:19 PM, Jeehoon Kang via llvm-dev wrote:
>
> Dear llvm-dev,
>
>
> Hi! We're collecting mis-compilation bugs in gvn and mem2reg since
> 3.7.1. Specifically, We're interested in bugs in the following files:
>
> llvm/lib/Transforms/Scalar/GVN.cpp
> llvm/lib/Transforms/Utils/Promot...
2018 Apr 10
2
Miscompilation bugs in GVN.cpp and PromoteMemoryToRegister.cpp?
...erested in bugs in the following files:
llvm/lib/Transforms/Scalar/GVN.cpp
llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
We checked all reports in the LLVM bugzilla (https://bugs.llvm.org/), so
I'd like to ask if you know any such a bug that is not reported in the
bugzilla.
Thanks,
Jeehoon Kang
--
Jeehoon Kang (Ph.D. student) <http://sf.snu.ac.kr/jeehoon.kang>
Software Foundations Laboratory <http://sf.snu.ac.kr>
Seoul National University <http://www.snu.ac.kr>
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2018 Apr 10
0
Miscompilation bugs in GVN.cpp and PromoteMemoryToRegister.cpp?
On Tue, Apr 10, 2018 at 3:09 PM, Daniel Berlin via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
>
>
> On Tue, Apr 10, 2018 at 10:28 AM, Friedman, Eli via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> On 4/9/2018 8:19 PM, Jeehoon Kang via llvm-dev wrote:
>>
>> Dear llvm-dev,
>>
>>
>> Hi! We're collecting mis-compilation bugs in gvn and mem2reg since
>> 3.7.1. Specifically, We're interested in bugs in the following files:
>>
>> llvm/lib/Transforms/Scalar/GVN.cpp
>&...
2018 Apr 10
0
Miscompilation bugs in GVN.cpp and PromoteMemoryToRegister.cpp?
On 4/9/2018 8:19 PM, Jeehoon Kang via llvm-dev wrote:
> Dear llvm-dev,
>
>
> Hi! We're collecting mis-compilation bugs in gvn and mem2reg since
> 3.7.1. Specifically, We're interested in bugs in the following files:
>
> llvm/lib/Transforms/Scalar/GVN.cpp
> llvm/lib/Transforms/Utils/PromoteMemo...