search for: je_4

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several

...egClass); // Set the indice BuildMI(*MBB, MI, db, TII->get(X86::MOV64rr)).addReg(reg).addReg(X86::RSP); // Create the for loop condition BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::CMP64rr)).addReg(reg).addReg(X86::RBP); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::JE_4)).addMBB(MBB_end); // Update phi node BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::PHI), reg).addReg(reg).addMBB(MBB).addReg(reg).addMBB(MBB_erase); // Erase content of stack BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::MOV32mi)) .addReg(reg).addImm(1).addReg(0).ad...

...BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::PHI), regB).addReg(regA).addMBB(MBB).addReg(regC).addMBB(MBB_erase); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::CMP64rr)).addReg(regB).addReg(X86::RBP); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::JE_4)).addMBB(MBB_end); // mov dword[reg], 0x0 BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::MOV32mi)).addReg(regB).addImm(1).addReg(0).addImm(0).addReg(0).addImm(0); BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::ADD64ri32), regC).addReg(regB).addImm(8); B...

...B %entry > Live Ins: %RDI > %vreg7<def> = COPY %RDI; GR64:%vreg7 > %vreg1<def> = MOV64rm %vreg7, 1, %noreg, 8, %noreg; mem:LD8[%args.03](tbaa=<badref>) GR64:%vreg1,%vreg7 > TEST64rr %vreg1, %vreg1, %EFLAGS<imp-def>; GR64:%vreg1 > JE_4 <BB#3>, %EFLAGS<imp-use,kill> > Successors according to CFG: BB#3(12) BB#1(20) > > BB#1: > Predecessors according to CFG: BB#0 > %vreg9<def> = COPY %vreg1; GR64:%vreg9,%vreg1 > %vreg10<def> = COPY %vreg7; GR64:%vreg10,%vreg7 >...

...vreg7 Successors according to CFG: BB#1 BB#1: derived from LLVM BB %entry Predecessors according to CFG: BB#0 BB#2 %vreg8<def> = PHI %vreg7, <BB#0>, %vreg9, <BB#2>; GR64:%vreg8,%vreg7,%vreg9 CMP64rr %vreg8, %RBP, %EFLAGS<imp-def>; GR64:%vreg8 JE_4 <BB#3>, %EFLAGS<imp-use> Successors according to CFG: BB#2 BB#3 BB#2: derived from LLVM BB %entry Predecessors according to CFG: BB#1 MOV32mi %vreg8, 1, %noreg, 0, %noreg, 0; GR64:%vreg8 %vreg9<def,tied1> = ADD64ri32 %vreg8<tied0>, 8, %EFLAGS<imp-...