search for: jcc

...c., and anything we build fails at the linking stage. My best attempt at this so far is a small patch to X86AsmParser.cpp - just taking any Intel expression with no specified base register and switching it to use RIP - and this works alright. There's at least one exception: it breaks the "jcc" instructions, at least "jcc <label>". The issue seems to be that the "jcc" family exclusively takes a relative offset, never an absolute reference... so adding a base register causes the operand not to match. ("jcc" is always RIP-relative anyway.) I'm...

...to mimic ml.exe's approach; a reference to a symbol in another section should use the relative addressing mode. My first attempt to fix this was very clumsy - when in MASM mode, I forced all expressions without a base register to presume RIP. Unfortunately, that breaks any attempt to use "jcc", since it turns label references into absolute memory references with a base register (and the "jcc" family doesn't accept absolute memory operands). Any suggestions for how I can fix the issue described here without breaking "jcc"? On Tue, Jan 21, 2020 at 3:43 PM Eli...

...to mimic ml.exe's approach; a reference to a symbol in another section should use the relative addressing mode. My first attempt to fix this was very clumsy - when in MASM mode, I forced all expressions without a base register to presume RIP. Unfortunately, that breaks any attempt to use "jcc", since it turns label references into absolute memory references with a base register (and the "jcc" family doesn't accept absolute memory operands). Any suggestions for how I can fix the issue described here without breaking "jcc"? On Tue, Jan 21, 2020 at 3:43 PM Eli...

...nicely, and I've until now found the answer to all my questions directly in the LLVM source code, or in the documentation. However, I'm having problems with the AsmBackend class and the handling of fixups. The processor I'm working with has a single conditional branch instruction, JCC, that takes an IP-relative 9-bit immediate offset as operand. A second version of the instruction takes a register as operand and can therefore jump to any 32-bit address. In AsmBackend, there are methods for relaxing instructions, that I wanted to use to replace "JCC imm9" instructio...

...t general assembly work, it may be difficult to do more optimization. This makes me concerned of another thing: Intel's Jump Condition Code Erratum. https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf Put it in the simplest way, a Jcc instruction whose address ≡ 30 or 31 (mod 32) should be avoided. There are assembler level (MC) mitigations (function sections are overaligned to 32), but because we use basic block sections (sh_addralign<32) and need reordering, we have to redo some work at the linking stage. After losing the...

...GNU/Linux and wine-1.0.1. I installed jre for windows in wine and run .bat program that run a java SWT application taht access a database db2. After running for a few moments an error is generated, this error occurs only under wine. DB2 use port 50000. Application.commit Text : [ibm][db2][jcc][t4][2030][11211] A communication error has been detected. Communication protocol being used: TCP/IP. Communication API being used: SOCKETS. Location where the error was detected: Reply.fill(). Communication function detecting the error: InputStream.read(). Protocol specific error codes Read time...

...at gmail.com>; Eli Friedman <efriedma at quicinc.com> Cc: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev <llvm-dev at lists.llvm.org>; Zhang, Annita <annita.zhang at intel.com>; Craig Topper <craig.topper at intel.com> Subject: [EXT] Re: [llvm-dev] Status of Intel JCC Mitigations and Next Steps The slightly unexpected bit for me in these responses is the willingness to accept layout changes if documented. Let me lay out some options, which of these seem reasonable? 1) Default to automatic padding, provide option to disable, document where padding is inserted...

...ent:* Tuesday, March 24, 2020 3:55 PM > *To:* llvm-dev <llvm-dev at lists.llvm.org> > *Cc:* Luo, Yuanke <yuanke.luo at intel.com>; Zhang, Annita < > annita.zhang at intel.com>; Craig Topper <craig.topper at intel.com> > *Subject:* [EXT] [llvm-dev] Status of Intel JCC Mitigations and Next Steps > > > > TLDR - We have a choice to make about assembler support, and a > disagreement about how to move forward. Community input needed. > > > > Background > > Intel has a hardware bug in Skylake and later whose mitigation requires > p...

...I debug this? ---------------------------Complete Output:---------------------- # Machine code for f(): Live Ins: R15W in VR#1025 R14W in VR#1026 Live Outs: R15W entry: 0xa244bd4, LLVM BB @0xa1f0c10, ID#0: Live Ins: %R15W %R14W CMP16rr %R14W<kill>, %R15W<kill>, %SRW<imp-def> JCC mbb<return,0xa244d04>, 5, %SRW<imp-use> Successors according to CFG: 0xa244d04 (#4) 0xa244c20 (#1) if.else: 0xa244c20, LLVM BB @0xa1f0a08, ID#1: Live Ins: %R15W %R15B Predecessors according to CFG: 0xa244bd4 (#0) CMP16ir -21, %R15W, %SRW<imp-def> JCC mbb<if.end7,0xa2...

TLDR - We have a choice to make about assembler support, and a disagreement about how to move forward.  Community input needed. Background Intel has a hardware bug in Skylake and later whose mitigation requires padding of branches to avoid performance degradation. Background here:

...t into different llvm functions we might be able to make that work but I'm skeptical. My main concern is that cold/frozen code nearly always uses a bunch of values from the main code path that branched to it, and if the overhead of getting from main to cold/frozen is more than a single jmp/jcc instruction (on x86) that's going to be a dealbreaker. Does this sound doable, and is it something you'd be ok having in llvm? If we can come up with a good design my team is happy to do the actual work, though if anyone else is interested in doing it we certainly won't complain :)....

Hi all! Does anyone know if a vector autoregression package is avaialable that allows binary variables as part of the endogenous system? I'm looking for something along the lines of what is implemented in "Dynamic Forecasts of Qualitative Variables: A Qual VAR Model of US Recessions" by Michael Dueker, 2003, Fed Reserve Bank of St. Louis. Another possibility is the autoregressive

Hello, I seem to have issues with setting the driver: My code: library(RJDBC) getStatic <- function() { # set driver driverClass <- JDBC("com.ibm.db2.jcc.DB2Driver","someClassPath.jar","'") conn <- dbConnect(driverClass,"serverName") etc etc } I get this error > data <-getData() Exception in thread "main" java.sql.SQLException: No suitable driver at java.sql.DriverManage...

...rror. As far as I can tell it's only the win2000 and NT4 workstations there have this problem - and not all of them, I can't see any patteren in this error. I would really hate to go back to the prev. version af samba - but if continues I have no choise....:(( Regards Jesper Christensen jcc@pop3.bit.dk

...s, as far as I can tell, there's no descriptive list of the channels anywhere. +address: Log the address of the command being executed to form this log so people can reference it in a dissassembly of the program. +jumps: Log jumps taken. This would help in finding what cmp/test is causing the jCC to the error so I can nop/jmp it as necessary. It's not a legitimate error in my case anyway, probably just some other "anti-hacking" technique that really only keeps you from running legitimate programs alongside the damn thing. And lastly, some kind of debug config tool would be s...

Hi All, Does any one know if attended call transfer has been added into the STABLE release of asterisk yet? Potentially using a mix of phones would create confusion in a user base, any ideas on attended transfer or how to achieve this / mods to dial plan etc would be greatly appreciated. I have been on an almost vertical learning curve with Asterisk and Linux for 6 months this is just

Hi guys, I need to move an lvm based domU from one dom0 to another dom0. How do you guys do ths? xm save/restore doesnt have the option to specify lvm target as the storage. Thanks Chris _______________________________________________ Xen-users mailing list Xen-users@lists.xensource.com http://lists.xensource.com/xen-users

...reg0<kill>; mem:ST4[%c.addr] GR32:%vreg0 MOV32mr <fi#2>, 0, %vreg1<kill>; mem:ST4[%d.addr] GR32:%vreg1 %vreg2<def> = MOV32rm <fi#1>, 0; mem:LD4[%c.addr] GR32:%vreg2 %vreg3<def> = CMPfri %vreg2<kill>, 0; SR1:%vreg3 GR32:%vreg2 JCC %vreg3<kill>, <BB#2>; SR1:%vreg3 JMP <BB#1>, %R0<imp-use> Successors according to CFG: BB#1(20) BB#2(12) BB#1: derived from LLVM BB %if.then Predecessors according to CFG: BB#0 %vreg5<def> = MOV32rm <fi#2>, 0; mem:LD4[%d.addr] GR32:%vreg5...

This is a small series getting rid of paravirt patching by switching completely to alternative patching for the same functionality. The basic idea is to add the capability to switch from indirect to direct calls via a special alternative patching option. This removes _some_ of the paravirt macro maze, but most of it needs to stay due to the need of hiding the call instructions from the compiler

This is a small series getting rid of paravirt patching by switching completely to alternative patching for the same functionality. The basic idea is to add the capability to switch from indirect to direct calls via a special alternative patching option. This removes _some_ of the paravirt macro maze, but most of it needs to stay due to the need of hiding the call instructions from the compiler