search for: ivybridge

After resuming more than once on battery these HP Ivybridge laptops, the XHCI devices stop working. Have anyone seen this before? I wanted to check before diving in deeper. Let me know if you have any ideas. Thanks! Facts - Xen 4.0.3, Linux 3.2.7 PVOPs - Happens on HP Ivybridge. Doesn''t happen on very similar HP Sandybridge Clash system. - Happ...

On Mar 19, 2012, at 6:11 PM, Sarah Sharp wrote: > On Mon, Mar 19, 2012 at 05:05:47PM -0400, Tom Goetz wrote: >> On Mar 19, 2012, at 12:45 PM, Tom Goetz wrote: >>> On Mar 19, 2012, at 9:32 AM, Tom Goetz wrote: >>> I''ve just found that if the xHCI is in D3, has a USB device plugged in, and is not waking up, it will wake up when another device in D3 wakes up.

Hi, According to virsh capabilities I only have the following cpu features: <cpu> <arch>x86_64</arch> <model>IvyBridge-IBRS</model> <vendor>Intel</vendor> <microcode version='32'/> <topology sockets='1' cores='4' threads='1'/> <feature name='ds'/> <feature name='acpi'/> <feature name='...

...des and add more comments. >> - Test for X86_FEATURE_HYPERVISOR CPU feature bit to enable/disable >> unfair lock. >> - Reduce unfair lock slowpath lock stealing frequency depending >> on its distance from the queue head. >> - Add performance data for IvyBridge-EX CPU. > FYI, your v7 patch with 32 VCPUs (on a 32 cpu socket machine) on an > HVM guest under Xen after a while stops working. The workload > is doing 'make -j32' on the Linux kernel. > > Completely unresponsive. Thoughts? > Thank for reporting that. I haven't done...

...des and add more comments. >> - Test for X86_FEATURE_HYPERVISOR CPU feature bit to enable/disable >> unfair lock. >> - Reduce unfair lock slowpath lock stealing frequency depending >> on its distance from the queue head. >> - Add performance data for IvyBridge-EX CPU. > FYI, your v7 patch with 32 VCPUs (on a 32 cpu socket machine) on an > HVM guest under Xen after a while stops working. The workload > is doing 'make -j32' on the Linux kernel. > > Completely unresponsive. Thoughts? > Thank for reporting that. I haven't done...

...argetFeatures() { (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX (Family == 6 && Model == 0x2A) || // SandyBridge (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E* - (Family == 6 && Model == 0x3A))) {// IvyBridge + (Family == 6 && Model == 0x3A) || // IvyBridge + (Family == 6 && Model == 0x3E) || // IvyBridge EP + (Family == 6 && Model == 0x3C) || // Haswell + (Family == 6 && Model == 0x3F) || // ... + (Family == 6 && Model == 0...

...m.git 33c352b3eda89abc24e7511d9045fa2e499a42e3) Target: x86_64-unknown-linux-gnu Thread model: posix llc version: LLVM (http://llvm.org/): LLVM version 3.7.1 Optimized build. Built Apr 4 2016 (15:04:44). Default target: x86_64-unknown-linux-gnu Host CPU: ivybridge Registered Targets: aarch64 - AArch64 (little endian) aarch64_be - AArch64 (big endian) amdgcn - AMD GCN GPUs arm - ARM arm64 - ARM64 (little endian) armeb - ARM (big endian) bpf - BPF (host endian)...

I agree with Tim, you need to implement a GetCpuIDAndInfoEx function in Host.cpp and pass the correct value to ecx. Also you need to verify that 7 is a valid leaf because an invalid leaf is defined to return the highest supported leaf on that processor. So if a processor supports say leaf 6 and not leaf 7, then an access leaf 7 will return the data from leaf 6 causing unrelated bits to be

...argetFeatures() { (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX (Family == 6 && Model == 0x2A) || // SandyBridge (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E* - (Family == 6 && Model == 0x3A))) {// IvyBridge + (Family == 6 && Model == 0x3A) || // IvyBridge + (Family == 6 && Model == 0x3C))) {// Haswell IsUAMemFast = true; ToggleFeature(X86::FeatureFastUAMem); } -- 1.8.3.4 (Apple Git-47)

...> - Test for X86_FEATURE_HYPERVISOR CPU feature bit to enable/disable > >>> unfair lock. > >>> - Reduce unfair lock slowpath lock stealing frequency depending > >>> on its distance from the queue head. > >>> - Add performance data for IvyBridge-EX CPU. > >>FYI, your v7 patch with 32 VCPUs (on a 32 cpu socket machine) on an > >>HVM guest under Xen after a while stops working. The workload > >>is doing 'make -j32' on the Linux kernel. > >> > >>Completely unresponsive. Thoughts? > >&...

...> - Test for X86_FEATURE_HYPERVISOR CPU feature bit to enable/disable > >>> unfair lock. > >>> - Reduce unfair lock slowpath lock stealing frequency depending > >>> on its distance from the queue head. > >>> - Add performance data for IvyBridge-EX CPU. > >>FYI, your v7 patch with 32 VCPUs (on a 32 cpu socket machine) on an > >>HVM guest under Xen after a while stops working. The workload > >>is doing 'make -j32' on the Linux kernel. > >> > >>Completely unresponsive. Thoughts? > >&...

Johannes, I tried the last one and it gave me this: error: unknown target CPU 'XYZ' note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, b...

...efficiently Johannes, I tried the last one and it gave me this: error: unknown target CPU 'XYZ' note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, b...

Hi All, We did a round testing for Xen 4.2 RC1 (CS#25692) with Linux 3.4.7 dom0. We covered VT-d, SR-IOV, Power Management, TXT, IVB new features, HSW new features. We covered many cases for HVM guests (both Redhat Linux and MS Windows guest). We tested on Westmere-EP, SandyBridge-EP, IvyBridge desktop, and Haswell hardware platforms. We found no new issues, and verified 1 fixed bug. Fixed bug (1): 1. parameter ''maxvcpus'' causes hvm guest boots up with wrong vcpu number http://bugzilla.xen.org/bugzilla/show_bug.cgi?id=1825 -- Fixed by Yang from Intel. The following are...

Hi Adam, > OK. I know the reason you cannot reproduce it, before posting > the patch I've decided to check for AVX before checking AVX2, > just not to cpuid AVX2 when we don't have AVX1 anyway. I suspect it was also incompetence on my part. Given the differences I'm seeing now I can't believe there'd be *no* difference in my tests if I'd done them properly.

...;> Thread model: posix >> >> llc version: >> >> LLVM (http://llvm.org/): >> LLVM version 3.7.1 >> Optimized build. >> Built Apr 4 2016 (15:04:44). >> Default target: x86_64-unknown-linux-gnu >> Host CPU: ivybridge >> >> Registered Targets: >> aarch64 - AArch64 (little endian) >> aarch64_be - AArch64 (big endian) >> amdgcn - AMD GCN GPUs >> arm - ARM >> arm64 - ARM64 (little endian) >> arme...

There are basically three issues we''re waiting to sort out (see below for more info): * XSA-55 * cpu hotplug in qemu-upsream * The MMIO hole issue Unfortuantely, there is considerable uncertainty about how long it will take for each of those to complete. We''re hoping to be able to release maybe on the 19th, This information will be mirrored on the Xen 4.3 Roadmap wiki page:

...hey do remind me of the scheduler code in 2.6.x which was based on heuristics - and eventually ripped out. So are these optimizations based on turning off certain hardware features? Say hardware prefetching? What I am getting at - can the hardware do this at some point (or perhaps already does on IvyBridge-EX?) - that is prefetch the per-cpu areas so they are always hot? And rendering this optimization not needed? Thanks!

...hey do remind me of the scheduler code in 2.6.x which was based on heuristics - and eventually ripped out. So are these optimizations based on turning off certain hardware features? Say hardware prefetching? What I am getting at - can the hardware do this at some point (or perhaps already does on IvyBridge-EX?) - that is prefetch the per-cpu areas so they are always hot? And rendering this optimization not needed? Thanks!

...I tried the last one and it gave me this: > > > error: unknown target CPU 'XYZ' > note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, > silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, > westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, > core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, > cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, > athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, > barcelona, btver1, btver2, bdver...