Displaying 4 results from an estimated 4 matches for "ivmd".
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2017 Sep 06
2
[RFC] virtio-iommu version 0.4
...nd report them
to the guest as MEM_T_BYPASS. However, when we start handing page table
control over to the guest, the host won't be in control of IOVA->GPA
mappings and will need to gracefully ask the guest to do it.
I'm not aware of any firmware description resembling Intel RMRR or AMD
IVMD on ARM platforms. I do think ARM platforms could need MEM_T_IDENTITY
for requesting the guest to map MSI windows when page-table handover is in
use (MSI addresses are translated by the physical SMMU, so a IOVA->GPA
mapping must be installed by the guest). But since a vSMMU would need a
solution...
2017 Sep 06
2
[RFC] virtio-iommu version 0.4
...nd report them
to the guest as MEM_T_BYPASS. However, when we start handing page table
control over to the guest, the host won't be in control of IOVA->GPA
mappings and will need to gracefully ask the guest to do it.
I'm not aware of any firmware description resembling Intel RMRR or AMD
IVMD on ARM platforms. I do think ARM platforms could need MEM_T_IDENTITY
for requesting the guest to map MSI windows when page-table handover is in
use (MSI addresses are translated by the physical SMMU, so a IOVA->GPA
mapping must be installed by the guest). But since a vSMMU would need a
solution...
2017 Sep 21
0
[RFC] virtio-iommu version 0.4
...e",
correct?
Then yes, I think above works.
> table
> control over to the guest, the host won't be in control of IOVA->GPA
> mappings and will need to gracefully ask the guest to do it.
>
> I'm not aware of any firmware description resembling Intel RMRR or AMD
> IVMD on ARM platforms. I do think ARM platforms could need
> MEM_T_IDENTITY
> for requesting the guest to map MSI windows when page-table handover is
> in
> use (MSI addresses are translated by the physical SMMU, so a IOVA->GPA
> mapping must be installed by the guest). But since a vSM...
2011 Sep 23
0
[xen-unstable test] 9061: regressions - FAIL
...e0259239822
user: Jan Beulich <jbeulich@suse.com>
date: Thu Sep 22 18:28:03 2011 +0100
PCI multi-seg: AMD-IOMMU specific adjustments
There are two places here where it is entirely unclear to me where the
necessary PCI segment number should be taken from (as IVMD descriptors
don''t have such, only IVHD ones do). AMD confirmed that for the time
being it is acceptable to imply that only segment 0 exists.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
changeset: 23862:85418e168527
user: Jan Beulich <jbeulich...