Displaying 4 results from an estimated 4 matches for "itstate".
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2017 Nov 11
2
Update control flow graph when splitting a machine basic block?
...implicit %r0, implicit %r1, implicit-def %sp, implicit-def %r0, debug-location !25
DBG_VALUE 2, 0, !17, !18, debug-location !27
DBG_VALUE debug-use %r0, debug-use _, !16, !18, debug-location !26
tCMPi8 %r0, 2, 14, _, implicit-def %cpsr, debug-location !32
t2IT 11, 28, implicit-def %itstate
%r0 = tMOVi8 _, 1, 11, %cpsr, implicit %r0, implicit %itstate
tPOP_RET 11, %cpsr, def %r4, def %r6, def %r7, def %pc, implicit %r0, implicit %r4, implicit killed %itstate, debug-location !44
%r1 = t2MOVi 2, 14, _, _
t2B %bb.3.for.body, 14, _
Note that a terminator tPOP_RET is befor...
2017 Nov 11
2
Update control flow graph when splitting a machine basic block?
> The right way to update the CFG very much depends on how you're
> transforming it.
I would like to export the CFG for control flow checking.
Theoretically, it should be possible for a compiler to know every target of every control flow instruction, except for computed targets that are not known at compile-time.
When a machine basic block is split between two branches, as shown below:
2015 Sep 17
2
Register Number
...The 0x01 would be the
encoding used in generating the binary.
The D0 has id 14 on ARM because there are 13 other registers preceding it:
namespace ARM {
enum {
NoRegister,
APSR = 1,
APSR_NZCV = 2,
CPSR = 3,
FPEXC = 4,
FPINST = 5,
FPSCR = 6,
FPSCR_NZCV = 7,
FPSID = 8,
ITSTATE = 9,
LR = 10,
PC = 11,
SP = 12,
SPSR = 13,
D0 = 14,
...
-Krzysztof
--
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2015 Sep 17
2
Register Number
Dear all,
in my TestRegisterInfo.td file, I defined a register like this:
class TestReg<bits<6> enc, string name> : Register<name> {
let HWEncoding{5-0} = enc;
let Namespace = "TEST";
}
def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>;
but when I compile, the result I have in TestGenAsmMatcher.inc is this:
case 'd': // 7