Displaying 3 results from an estimated 3 matches for "itinieraries".
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2011 Apr 14
0
[LLVMdev] Fwd: LLVM Scheduler and Itinieraries: Negative latency?
Forwarding to llvm-dev...
---------- Forwarded message ----------
From: Magnus Pettersson <mangepe at gmail.com>
Date: Thu, Apr 14, 2011 at 21:33
Subject: Re: [LLVMdev] LLVM Scheduler and Itinieraries: Negative latency?
To: Anton Korobeynikov <anton at korobeynikov.info>
Hello Anton,
I am trying to model a fairly simple five stage pipelined processor.
The problem is that some instructions need the last stage (write back)
to be finished so the correct operand is selected for a following
i...
2011 Apr 14
0
[LLVMdev] LLVM Scheduler and Itinieraries: Negative latency?
Hello Magnus,
> I am trying to model a fairly simple five stage pipelined processor.
Ok.
> The problem is that some instructions need the last stage (write back) to be
> finished so the correct operand is selected for a following instruction in
> stage 3.
Ok, this is pretty typical.
> machine cycles and higher values for when the result is ready (3) and when
> the operands are
2011 Apr 14
3
[LLVMdev] LLVM Scheduler and Itinieraries: Negative latency?
Hello,
While trying to create back end in LLVM I have stumbled upon a problem
I have trouble to get past, hopefully someone can give me hints on
what I am doing wrong. The problem is that the assertion in the file
ScheduleDAGList.cpp row 187 is triggered: "Negative latency". How does
this happen?
As background:
My target has one issue unit, therefore my Schedule.td file only