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...using director, you can issue `doveadm quota recalc -A` on > director, which will then direct it to correct backend. > > For this to work, it requires that you setup doveadm server on the backend, > and configure doveadm_port and doveadm_password on director. It also either > needs iteratable user database on director, or a list of users in a file, > which you can provide with option -F. > > Aki Hi Aki, Nice to know! The quota plugin has to be configured on the frontends? With which backend? Right now the "quota" subcommands are not recognised. Thanks-- *Sim...

...another point: I want to switch to count backend (now I'm using maildir++). With this backend, the quota is memorized on the indexes, but if I make all the recalc on one backend only, the others will not have the correct quota on their indexes. Right now I've written a python script that iterates over the users, asks to the frontend (via doveadm http) which is the current backend, and then connect (again, doveadm http) to that to perform the recalculation. A bit slow but working. -- *Simone Lazzaris* *Qcom S.p.A. a Socio Unico* Via Roggia Vignola, 9 | 24047 Treviglio (BG)T +39 0363...

We received no replies to this email that we sent a few days ago. We're not sure why. If we miss something that is obvious to everybody, kindly point it out. We ?ould like to get iteration working, to be able to mass-delete specific emails from all mailboxes, in case of for example received virusses... Here is my question again: Hi, User iteration doesn't work, we're getting: > auth: Error: Trying to iterate users, but userdbs don't support it The way I unders...

...g register pressure (fast or ILP), while it makes things worse when the SD scheduler is relatively good at reducing register pressure (BURR or source). > > Execution Times > --------------------- > Execution times were measured by running the benchmarks on an x86-64 machine with 5 or 9 iterations per benchmark as indicated below (in most cases, no significant difference was observed between 9 iterations (which take about two days) and 5 iterations (which take about one day)). The differences in the table below are calculated relative to the source scheduler. The %Diff Max (Min) is the m...

Hi all, I 'd like to fetch a list of structures, and found that it could be done via LLVMContextImpl *pImpl = Context.pImpl; pImpl->AnonStructTypes This however needs the inclusion of LLVMContextImpl.h, which is not contained in the includes dir, but in the lib/IR dir (next to the .cpp files) and is not installed under /usr/local/include... Whats the reason for this? Isn't it

On 07.07.2017 10:33, mj wrote: > We received no replies to this email that we sent a few days ago. > We're not sure why. If we miss something that is obvious to everybody, > kindly point it out. > We ?ould like to get iteration working, to be able to mass-delete > specific emails from all mailboxes, in case of for example received > virusses... > > Here is my question again: > > Hi, > > User iteration doesn't work, we're getting: >> auth: Error: Trying to iterate users, but userdbs...

...want to switch to count backend (now I'm using maildir++). With this backend, the quota is memorized on the indexes, but if I make all the recalc on one backend only, the others will not have the correct quota on their indexes. > > > Right now I've written a python script that iterates over the users, asks to the frontend (via doveadm http) which is the current backend, and then connect (again, doveadm http) to that to perform the recalculation. > > A bit slow but working. > > > -- > > Simone Lazzaris If you are using director, you can issue `dove...

...g register pressure (fast or ILP), while it makes things worse when the SD scheduler is relatively good at reducing register pressure (BURR or source). > > Execution Times > --------------------- > Execution times were measured by running the benchmarks on an x86-64 machine with 5 or 9 iterations per benchmark as indicated below (in most cases, no significant difference was observed between 9 iterations (which take about two days) and 5 iterations (which take about one day)). The differences in the table below are calculated relative to the source scheduler. The %Diff Max (Min) is the m...

...t;>>>> mean setting mas.index/mas.last to the correct value. There is a node & >>>>> offset saved in the maple state that needs to be in the correct >>>>> location. If you store to that node then the node may be replaced, so >>>>> other iterators that you have may become stale, but the one you used >>>>> execute the store operation will now point to the new node with the new >>>>> entry. >>>>> >>>>>> >>>>>> I already provided this example in a separate mail...

...ely weak at reducing register pressure (fast or ILP), while it makes things worse when the SD scheduler is relatively good at reducing register pressure (BURR or source). Execution Times --------------------- Execution times were measured by running the benchmarks on an x86-64 machine with 5 or 9 iterations per benchmark as indicated below (in most cases, no significant difference was observed between 9 iterations (which take about two days) and 5 iterations (which take about one day)). The differences in the table below are calculated relative to the source scheduler. The %Diff Max (Min) is the m...

On Jul 2, 2013, at 2:35 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Thank you for the answers! We are currently trying to test the MI scheduler. We are using LLVM 3.3 with Dragon Egg 3.3 on an x86-64 machine. So far, we have run one SPEC CPU2006 test with the MI scheduler enabled using the option -fplugin-arg-dragonegg-llvm-option='-enable-misched:true' with -O3.

...on, and that doesn't just >>> mean setting mas.index/mas.last to the correct value. There is a node & >>> offset saved in the maple state that needs to be in the correct >>> location. If you store to that node then the node may be replaced, so >>> other iterators that you have may become stale, but the one you used >>> execute the store operation will now point to the new node with the new >>> entry. >>> >>>> >>>> I already provided this example in a separate mail thread, but it may makes >>>&gt...

...t;>>> @@ -466,6 +466,37 @@ DRM MM Range Allocator Function References >>>> .. kernel-doc:: drivers/gpu/drm/drm_mm.c >>>> :export: >>> ... >>> >>>> + >>>> +/** >>>> + * drm_gpuva_remove_iter - removes the iterators current element >>>> + * @it: the &drm_gpuva_iterator >>>> + * >>>> + * This removes the element the iterator currently points to. >>>> + */ >>>> +void >>>> +drm_gpuva_iter_remove(struct drm_gpuva_iterator *it) >>&...

Thank you for the answers! We are currently trying to test the MI scheduler. We are using LLVM 3.3 with Dragon Egg 3.3 on an x86-64 machine. So far, we have run one SPEC CPU2006 test with the MI scheduler enabled using the option -fplugin-arg-dragonegg-llvm-option='-enable-misched:true' with -O3. This enables the machine scheduler in addition to the SD scheduler. We have verified this by