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Hi I''m trying to monitor my multi ISP shorewall with swping, the script works fine, i can see in log when an ISP is down, the script restart shorewall and /etc/shorewall/isusable is called, however in the swping log after the shorewall restart i see again a route by ISP (even the ISP down), is it normal ? should i not see one route less? shorewall version 4.4.5.4-1. **** /etc/shorewall/provider *freenew 1024 1024 main eth2.303 8...

...eIntervals::getSpillWeight. Do we have to scale the values somehow there? > > Yes, BlockFrequency::getFrequency() is poorly named, it returns a fixpoint number. I think you should scale it to be relative to the entry block frequency. > > +LiveIntervals::getSpillWeight(bool isDef, bool isUse, BlockFrequency freq) { > + return (isDef + isUse) * freq.getFrequency(); > } > > This computation can overflow. Yep, I went down the easy route and converted it to floating point arithmetic. Is that OK here? > > @@ -178,9 +180,10 @@ bool SpillPlacement::runOnMachineFunction...

...13, at 10:48 AM, Benjamin Kramer <benny.kra at gmail.com> wrote: > [Splitting this out from the original thread to reduce noise in it] > > > On 17.06.2013, at 18:43, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >> +LiveIntervals::getSpillWeight(bool isDef, bool isUse, BlockFrequency freq) { >> + return (isDef + isUse) * freq.getFrequency(); >> } >> >> This computation can overflow. > > Yep, I went down the easy route and converted it to floating point arithmetic. Is that OK here? Yes, that should be fine. +LiveIntervals::getS...

Kalle: Your patch is similar to what I'd coded (and am testing, which means a couple of hours before I consider committing). Other than cosmetic changes and changing 'NULL' to '0' (it's an integer list, after all). This patch now causes new problems in the CellSPU backend (more stqd's and lqd's), so I have to investigate those before committing the patch.

...sting part is in LiveIntervals::getSpillWeight. Do we have to scale the values somehow there? Yes, BlockFrequency::getFrequency() is poorly named, it returns a fixpoint number. I think you should scale it to be relative to the entry block frequency. +LiveIntervals::getSpillWeight(bool isDef, bool isUse, BlockFrequency freq) { + return (isDef + isUse) * freq.getFrequency(); } This computation can overflow. @@ -178,9 +180,10 @@ bool SpillPlacement::runOnMachineFunction(MachineFunction &mf) { // Compute total ingoing and outgoing block frequencies for all bundles. BlockFrequency.res...

On 17.06.2013, at 15:56, Diego Novillo <dnovillo at google.com> wrote: > On 2013-06-15 16:39 , Benjamin Kramer wrote: >> Do you want to take over this effort or should I poke more at it? > > Since you've already started, it's easier if you poke more at it. Thanks. I've got a whole bunch of other things to go through. OK, will do. Jakob any comments on the

...sert at line 192, lib/CodeGen/RegisterScavenging.cpp that appears to get tripped on targets that don't have subregisters defined: bool SubUsed = false; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) if (isUsed(SubReg)) { SubUsed = true; break; } assert(SubUsed && "Using an undefined register!"); CellSPU does not define any subregisters; consequently, SubUsed will always be false and trip the assert. What's the intended behavior (before I...

Hello http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-1536 "Integer underflow in the file_printf function in the "file" program before 4.20 allows user-assisted attackers to execute arbitrary code via a file that triggers a heap-based buffer overflow." Is FreeBSD 5.x/6.x affected too? It looks the System has file 4.12. The port has 4.20. Regards, Thomas -- Terry

...::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

.../RegisterScavenging.cpp that > appears to get tripped on targets that don't have subregisters defined: > > bool SubUsed = false; > for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); > unsigned SubReg = *SubRegs; ++SubRegs) > if (isUsed(SubReg)) { > SubUsed = true; > break; > } > assert(SubUsed && "Using an undefined register!"); > > CellSPU does not define any subregisters; consequently, SubUsed will always > be false and trip the assert. What'...

...efore the one I'm processing. > > The following code snippet : > > > void R600ModifiersPropagation::substituteReg(MachineOperand &def_MO, unsigned new_reg, unsigned char flag) { > MachineOperand * MO = def_MO.getNextOperandForReg(); > while (MO && MO->isUse()) { > MachineOperand *next_MO = MO->getNextOperandForReg(); > MO->dump(); > > MO = next_MO; > } > } > > displays instructions that are before the one I'm passing as def_MO. I'm not sure if I should call some Analysis pass to enforce MachineOpe...

...:59 thebighonker dovecot: imap(ler): Panic: file > imap-sieve-storage.c: line 616: unreached > > I can provide more logs, but doing the same to (one of) the base > mailbox(es) does NOT garner > the message. > > > 600 can_discard = FALSE; > 601 switch (isuser->cur_cmd) { > 602 case IMAP_SIEVE_CMD_APPEND: > 603 cause = "APPEND"; > 604 can_discard = TRUE; > 605 break; > 606 case IMAP_SIEVE_CMD_COPY: > 607 case IMAP_SIEVE_CMD_MOV...

Hey, guys, could someone tell me some high level things about the version of linear scan that you use? 1) The heuristics for spilling seems to be: (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth besides not spilling defs that are immediatly followed by uses, do you do any other thing, such as, taking into consideration the size of the interval when spilling? 2) How do you avoid conflicts with machine registers already in the target code,...

...ot;Unknown opcode."); case SP::CALL: break; case SP::JMPLrr: case SP::JMPLri: assert(MI->getNumOperands() >= 2); const MachineOperand &Reg = MI->getOperand(0); assert(Reg.isReg() && "JMPL first operand is not a register."); assert(Reg.isUse() && "JMPL first operand is not a use."); RegUses.insert(Reg.getReg()); const MachineOperand &RegOrImm = MI->getOperand(1); if (RegOrImm.isImm()) break; assert(RegOrImm.isReg() && "JMPLrr second operand is not a register.");...

...nder Cygwin on Windows Server 2003 (SP1) with Apache 2.0. The Rails apps works fine when proxied through Apache and running under WebRick, but Mongrel seems unhappy about something. The Apache service is running as the "Local System" user and I''m starting Mongrel as "ISUser" which is an Active Directory user. When I invoke the following command: mongrel_rails start -h It returns the following error message: /usr/lib/ruby/gems/1.8/gems/mongrel-1.0.1-mswin32/lib/http11.so: Permission denied - /usr/lib/ruby/gems/1.8/gems/mongrel-1.0.1-mswin32/ lib/http11....

...e. That leaves a dangling pointer in the kills list, which is big trouble. I don't yet have a standalone test case which reproduces the problem, though I'll try to make one. So far this problem has only been visible in very large programs. I have a fix, which is to remove the "if (MO.isUse())" test around the code that updates the kills list, causing it to attempt to do this for both uses and defs, but I'd like to understand this problem better. Why are kills entries added for defs in the first place? Is it expected that there will always be uses to take over the kill from...

...erand corresponds to. These return an unsigned int "register number"; but I'm not sure how to identify which register actually corresponds to that number. Also, I will need to identify definitions and uses of registers in instructions. I see that MachineOperand has methods such as isUse(), isDef(), and isKill(), which sound like they might be relevant to what I'm doing; but neither the Doxygen nor the source are particularly helpful as to what they actually do. From the MachineInstr documentation, I gathered that instructions which define a value are always written so that th...

...(r12) instead of the scavenger. - If possible, an extra callee-saved register is spilled instead of allocating an emergency spill slot. - Finally, an emergency spill slot is only allocated if it is needed. >> I am afraid the assert is correct, you are ignoring the outer "if >> (!isUsed(Reg))..." > > Hmm.. didn't miss it. Just didn't understand it :) > So the problem is that a use-operation does not have its register marked > as used? I.e. something is badly broken? Exactly. If a register is not marked as used, the scavenger thinks it is free to be us...

...> >> The following code snippet : >> >> >> void R600ModifiersPropagation::substituteReg(MachineOperand &def_MO, > unsigned new_reg, unsigned char flag) { >>   MachineOperand * MO = def_MO.getNextOperandForReg(); >>   while (MO && MO->isUse()) { >>     MachineOperand *next_MO = MO->getNextOperandForReg(); >>     MO->dump(); >> >>     MO = next_MO; >>   } >> } >> >> displays instructions that are before the one I'm passing as def_MO. > I'm not sure if I should c...

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some