Displaying 6 results from an estimated 6 matches for "isunsafememoryobject".
2015 Jul 01
3
[LLVMdev] MIScheduler + AA: Missed scheduling opportunity in MIsNeedChainEdge. Bug?
...hineInstrs are ordered by a memory dependence. It first runs through the standard criteria (Do both instructions access memory? Does at least one store to memory? Is either access volatile? etc.), and finally queries AliasAnalysis if available.
Before reaching alias analysis, however, function isUnsafeMemoryObject pessimizes the result. In particular, isUnsafeMemoryObject returns true unless all of the pointer's underlying objects satisfy IsIdentifiedObject. This forces MIsNeedChainEdge to conservatively report true, even though AliasAnalysis could give a more precise answer in some situations. Furthe...
2016 Feb 03
2
[buildSchedGraph] memory dependencies
...dthB = MMOb->getSize();
+ int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
+ int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
+ int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
+ if (LowOffset + LowWidth <= HighOffset)
+ return false;
+ }
+
if (isUnsafeMemoryObject(MIa, MFI, DL) || isUnsafeMemoryObject(MIb,
MFI, DL))
return true;
2) The TBAA tags should separate the loads from the stores. In the MF I see
...
%vreg32<def> = L %vreg0, 56, %noreg;
mem:LD4[%src1(align=64)+56](align=8)(tbaa=!1) GR32Bit:%vreg32
ADDR64Bit:%vreg0
...
ST %vreg33, %vre...
2014 Dec 19
2
[LLVMdev] ScheduleDAGInstrs.cpp
Hi,
I write again regarding buildSchedGraph(), as I am still not happy about things there.
I have found at least two examples which do not work out:
1)
SU(2) Store "Value A"
SU(1) Store "Value A"
SU(0) Load "Value A"
If MIsNeedChainEdge() returns false for SU(0) and SU(1), SU(0) is inserted into RejectedMemNodes and removed from its MemUses SU list, as this
2015 Jan 30
2
[LLVMdev] [PATCH] Bugfix for missed dependency from store to load in buildSchedGraph().
...mber 19, 2014 1:51:44 PM
> Subject: RE: ScheduleDAGInstrs.cpp
>
> Hi Jonas,
>
> How is your target implementing areMemAccessesTriviallyDisjoint? The
> callback is there so that we don't get into the situation where the
> call to isIdentifiedObject (which is called from isUnsafeMemoryObject
> from MIsNeedChainEdge) results in the edge being added between two
> memory locations that the target can easily prove are different (e.g
> based on base register + index + offset, etc).
>
> Are you seeing the problem during pre-RA scheduling or post-RA
> scheduling?
>...
2015 Feb 10
2
[LLVMdev] [PATCH] Bugfix for missed dependency from store to load in buildSchedGraph().
...eDAGInstrs.cpp
> >
> > Hi Jonas,
> >
> > How is your target implementing areMemAccessesTriviallyDisjoint?
> > The
> > callback is there so that we don't get into the situation where the
> > call to isIdentifiedObject (which is called from
> > isUnsafeMemoryObject from MIsNeedChainEdge) results in the edge
> > being added between two memory locations that the target can easily
> > prove are different (e.g based on base register + index + offset,
> > etc).
> >
> > Are you seeing the problem during pre-RA scheduling or post-RA...
2014 Dec 16
3
[LLVMdev] ScheduleDAGInstrs.cpp
Hi,
Thank you for the reply.
>It looks to me like we can choose any subset of edges here and be correct. We're basically trying to prune/pinch the DAG edges here. They can easily blow up with AA sched. I would guess that isCtrl() edges are good ones to bypass because they could be a low-latecy edges, whereas true data dependencies from a load are expected to be >higher latency, so they