search for: isterminal

Doh. I missed the list in my first reply... Here's the replay of the conversation: ----- Renato: On 10 August 2015 at 14:05, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > --> %SP<def,tied1> = t2LDMIA_RET %SP<tied0>, pred:8, pred:%CPSR, > %R7<def>, %PC<def>, %SP<imp-use,undef>, %R7<imp-use,undef>, >

Chris Lattner wrote: > On Tue, 22 Jun 2004, Vladimir Prus wrote: > > First, I attach two files -- LLVM asm and the asm for my target. The > > problem with assembler is: on line 171 it uses register gr2, which is > > copied from gr6 above, on line 161. The only predecessor of this basic > > block is jump on line 90. The problem is that gr6 is not initialized in > >

On Wed, 23 Jun 2004, Vladimir Prus wrote: > Hmm.. this is what I have in td file already: > > let isTerminator = 1 in > def GOTO : Unknown<"goto">; > def IFEQ : Unknown<"if =0 goto">; > def IFNEQ : Unknown<"if <>0 goto">; > ..... > > Should this work? Nope, but try this: let isTerminator = 1 in {

Hello, The function ARMBaseInstrInfo::AnalyzeBranch contains the following piece of code: } else if (I->isReturn()) { // Returns can't be analyzed, but we should run cleanup. CantAnalyze = !isPredicated(I); } else { This could lead to cases where for a block that ends with a conditional return, AnalyzeBranch returns false (i.e. analyzed), both TBB and FBB are

Hi Andy, I have to resurrect an ancient question regarding scheduling boundaries. You might remember the reason for introduction of CanHandleTerminators to ScheduleDAGInstrs. In short, Hexagon is currently uses DAG construction method (buildSchedGraph) for several purposes, which includes region formation for general VLIW packetization/bundling. As such we need to handle pretty much all

On Feb 11, 2013, at 1:03 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Hi Andy, > > I have to resurrect an ancient question regarding scheduling boundaries. > > You might remember the reason for introduction of CanHandleTerminators to > ScheduleDAGInstrs. In short, Hexagon is currently uses DAG construction > method (buildSchedGraph) for several purposes,

Hi all, I'm currently working on implementing ACLE extensions for ARM. There are some memory barrier intrinsics, i.e.__dsb and __isb that require the compiler not to reorder instructions around their corresponding built-in intrinsics(__builtin_arm_dsb, __builtin_arm_isb), including non-memory-access instructions.[1] This is currently not possible. It is sometimes useful to prevent the

On Feb 8, 2013, at 12:28 PM, Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi> wrote: > On 02/08/2013 08:20 PM, Tobias Grosser wrote: >> That sounds elegant and seems to solve the correctness problems. > > There is no big difference here except that the memory instructions > would not need the metadata. > > I do not think the abundance of metadata is really the

Replying to my self here. It seems I was missing an isTerminator = 1 on the branch instruction in question, so LLVM didn't know that the instruction terminated a basic block. Does that make sense, or is just masking some other problem? Thanks, Andreas On 9/28/07, Andreas Fredriksson <deplinenoise at gmail.com> wrote: > Hi, > I'm trying to write up my little m68k backend

On Tue, 22 Jun 2004, Vladimir Prus wrote: > First, I attach two files -- LLVM asm and the asm for my target. The problem > with assembler is: on line 171 it uses register gr2, which is copied from gr6 > above, on line 161. The only predecessor of this basic block is jump on line > 90. The problem is that gr6 is not initialized in the interval from the > function entry till the

I'm analyzing the basic blocks of MachineInstructions that LLVM generates for my TargetMachine to try to reconstruct high-level flow control. I misunderstood the isTerminator property of an instruction to mean that it had to be at the end of a basic block, but now I've seen blocks that end with a conditional branch followed by an unconditional branch. I'm sure this depends

Hi Anton and Dale first thanks for your answers. On 8 Aug 2007, at 16:43, Anton Korobeynikov wrote: > Hello, Arnold. > >> Is there a way to indicate that the register the tail call >> instruction uses as destination needs to be valid after the callee >> saved registers have been restored? (some X86InstrInfo.td foo magic >> maybe ?) > It's wrong way to do the

Hello, Arnold. > Is there a way to indicate that the register the tail call > instruction uses as destination needs to be valid after the callee > saved registers have been restored? (some X86InstrInfo.td foo magic > maybe ?) It's wrong way to do the things. Because in this case you either violate the ABI for callee, or you're restricted to do tail call lowering only for

...amp;ValueMap, const char *NameSuffix, Function *F) { BasicBlock *NewBB = new BasicBlock("", F); if (BB->hasName()) NewBB->setName(BB->getName()+NameSuffix); bool hasCalls = false, hasDynamicAllocas = false, hasStaticAllocas = false, isTerminal =false; // Loop over all instructions, and copy them over. for (BasicBlock::const_iterator II = BB->begin(), IE = BB->end(); II != IE; ++II) { const Instruction *NwInst = cast<Instruction>((II)); Instruction *NewInst =...

On Thu, Mar 29, 2012 at 01:50:58PM -0500, Sergei Larin wrote: > Tom, > > What is in your isSchedulingBoundary? If it contains isLabel you might > need to disable that assert: > > assert(!MI->isTerminator() && !MI->isLabel() && > "Cannot schedule terminators or labels!"); > > Sergei Larin > > -- > Qualcomm

Tom, What is in your isSchedulingBoundary? If it contains isLabel you might need to disable that assert: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); Sergei Larin -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Original Message----- > From: Tom Stellard

On Tue, 8 Jun 2004, Vladimir Prus wrote: > While adding support for branch instructions in my backend, I run into a > trouble. The code to handle branches looks like: > The machine code after instruction selection is: > > entry (0x8681458): > %reg1024 = load <fi#-1> > %reg1025 = load <fi#-2> > setcc %reg1024, %reg1025 >

...const char *NameSuffix, Function *F) { > > BasicBlock *NewBB = new BasicBlock("", F); > if (BB->hasName()) NewBB->setName(BB->getName()+NameSuffix); > > bool hasCalls = false, hasDynamicAllocas = false, > hasStaticAllocas = false, isTerminal =false; > > // Loop over all instructions, and copy them over. > for (BasicBlock::const_iterator II = BB->begin(), IE = BB->end(); > II != IE; ++II) > { > const Instruction *NwInst = cast<Instruction>((II)); What...

Hi, I'm trying to write up my little m68k backend things have been going smoothly. I've been working with the x86 backend as a template, fixing things as I go. Now I've run into branches and I have a crash I don't really understand. Here's the sample IR I'm running llc on to generate assembly: define i32 @ilog2(i32 %x) { entry: %tmp718 = icmp eq i32 %x, 0

On Oct 15, 2008, at 11:38 AMPDT, Daniel M Gessel wrote: > I'm analyzing the basic blocks of MachineInstructions that LLVM > generates for my TargetMachine to try to reconstruct high-level flow > control. > > I misunderstood the isTerminator property of an instruction to mean > that it had to be at the end of a basic block, but now I've seen > blocks that end with a