search for: istailcall

...ion 42247) > +++ include/llvm/Target/TargetLowering.h (working copy) > @@ -851,8 +851,18 @@ > virtual std::pair<SDOperand, SDOperand> > LowerCallTo(SDOperand Chain, const Type *RetTy, bool > RetTyIsSigned, > bool isVarArg, unsigned CallingConv, bool isTailCall, > - SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); > + bool isNextInstRet, SDOperand Callee, ArgListTy &Args, > + SelectionDAG &DAG); > + // IsEligibleForTailCallElimination - Check whether the call is > eligible for &g...

...ionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5726,7 +5726,7 @@ SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI, } void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, - bool isTailCall, + bool isTailCall, bool isVarArg, MachineBasicBlock *LandingPad) { PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); FunctionType *FTy = cast<FunctionType>(PT->getElementType());...

...+++ include/llvm/Target/TargetLowering.h (working copy) >> @@ -851,8 +851,18 @@ >> virtual std::pair<SDOperand, SDOperand> >> LowerCallTo(SDOperand Chain, const Type *RetTy, bool >> RetTyIsSigned, >> bool isVarArg, unsigned CallingConv, bool isTailCall, >> - SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); >> + bool isNextInstRet, SDOperand Callee, ArgListTy &Args, >> + SelectionDAG &DAG); >> + // IsEligibleForTailCallElimination - Check whether the call is >...

...m/Target/TargetLowering.h (revision 42247) +++ include/llvm/Target/TargetLowering.h (working copy) @@ -851,8 +851,18 @@ virtual std::pair<SDOperand, SDOperand> LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, bool isVarArg, unsigned CallingConv, bool isTailCall, - SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); + bool isNextInstRet, SDOperand Callee, ArgListTy &Args, + SelectionDAG &DAG); + // IsEligibleForTailCallElimination - Check whether the call is eligible for + // tailcall eliminatio...

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...2285,13 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, if (GPR_idx != NumGPRs) { RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + if (!isTailCall) + MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + // Calculate and remember argument location. + else + CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, + TailCallArguments); + inM...

...tLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, > if (GPR_idx != NumGPRs) { > RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); > } else { > - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, > 0)); > + if (!isTailCall) > + MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, > NULL, 0)); > + // Calculate and remember argument location. > + else > + CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, > ArgOffset, > +...

Hello Dale, this is an updated version of the tail call optimization patch for powerpc. could you have a look at it? i added code to support ppc64 (untested, will try to get access to ppc64 on a friend's machine). incorporated evan's formatting suggestions. ;) will run another round of testing (llvm-test) on my powerpc g4/800 when i get the okay to commit. testing on this machine takes

...r<ISD::OutputArg, 32> &Outs = CLI.Outs; SmallVector<SDValue, 32> &OutVals = CLI.OutVals; SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; SDValue Chain = CLI.Chain; SDValue Callee = CLI.Callee; bool &isTailCall = CLI.IsTailCall; CallingConv::ID CallConv = CLI.CallConv; bool doesNotRet = CLI.DoesNotReturn; bool isVarArg = CLI.IsVarArg; The CallLoweringInfo struct now contains all parameters that were originally av...

...LL(SDOperand Op, SelectionDAG &DAG, >> if (GPR_idx != NumGPRs) { >> RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); >> } else { >> - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, >> 0)); >> + if (!isTailCall) >> + MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, >> NULL, 0)); >> + // Calculate and remember argument location. >> + else >> + CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, >> ArgOffset, >> +...

...t happens for most calls. We can only really transform a franction of those into real tail calls later. Thanks, so back to my original point: if we have to disable the CSR optimization on function that “may be tail called”, it would still be better IMO to do something like `llvm::any_of(callsites, isTailCall)` instead of IsEligibleForTailCallOptimization(). — Mehdi -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160628/75660b11/attachment.html>

...can only > really transform a franction of those into real tail calls later. > > > Thanks, so back to my original point: if we have to disable the CSR > optimization on function that “may be tail called”, it would still be > better IMO to do something like `llvm::any_of(callsites, isTailCall)` > instead of IsEligibleForTailCallOptimization(). > > — > Mehdi > > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160629/dc8cede9/attachment.html>

LLVM code base seems to be full of base/interface classes, which have methods like virtual SDValue LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue&g...

...tor BBI = MF.begin(), BBE = MF.end(); BBI != BBE; ++BBI) for (MachineBasicBlock::iterator MI = BBI->begin(), ME = BBI->end(); MI != ME; ++MI) if (MI->getDesc().isCall() && !isTailCall(MI)) VisitCallPoint(FI, MI); return false; } using Nicolas' patch [1] and his code in VMkit as a template [2]. My problem is that I am not sure how i should define the "isTailCall" function in order to be target-independent. Any advice is welcome! Thank you in advance, Yiannis...

...;' failed. This is what my LowerCALL looks like: SDOperand MCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { SDOperand Chain = Op.getOperand(0); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; assert(!isVarArg); bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; SDOperand Callee = Op.getOperand(4); MVT::ValueType RetVT= Op.Val->getValueType(0); unsigned NumOps = (Op.getNumOperands() - 5) / 2; std::string Name; if (GlobalAddressSDNode *G = dyn_cast<Glob...

...nd an email to llvmdev to warn owners of all > the out-of-tree targets about the ABI change. Of course! :) So, are people okay with the interface? This is basically just struct-ifying the parameters to TargetLowering::LowerCallTo/LowerCall. My main concerns are the handling of the InVals and IsTailCall variables. I left InVals as a separate parameter to LowerCall, since it is entirely produced by the implementation. IsTailCall remains in the struct since it is given a value before LowerCall, although the LowerCall implementation can change its value (hence not passing the struct by const-refere...

...SelectionDAG &DAG, + unsigned CC) { + DOUT << "LowerX86_32FastCCCallTo\n"; + SDOperand Chain = Op.getOperand(0); + bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))- >getValue() != 0; + bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))- >getValue() != 0; + SDOperand Callee = Op.getOperand(4); + //unsigned NumOps = (Op.getNumOperands() - 5) / 2; + + // Analyze operands of the call, assigning locations to each operand. + SmallVector<CCValAssign, 16> ArgLocs; +...

Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in

Thanks. This is going in the right direction IMHO. Obviously, please make sure you add comments to the data structure and convert all the targets first. Also, please don't forget to send an email to llvmdev to warn owners of all the out-of-tree targets about the ABI change. Evan On May 15, 2012, at 6:56 AM, Justin Holewinski <jholewinski at nvidia.com> wrote: > In response to this

...c80, Outs=@0x8046350, Fn=0x88c7838 <ARM_AAPCS_GHC>) at CallingConvLower.cpp:126 #6 0x088cb08a in llvm::ARMTargetLowering::LowerCall (this=0x92b4c58, Chain= {Node = 0x92d1b50, ResNo = 0}, Callee={Node = 0x92d1c60, ResNo = 0}, CallConv=llvm::CallingConv::GHC, isVarArg=false, isTailCall=@0x804656b, Outs=@0x8046350, OutVals=@0x8046230, Ins=@0x8045f30, dl={LineCol = 0, ScopeIdx = 0}, DAG=@0x92bdea8, InVals=@0x80461f0) at ARMISelLowering.cpp:1209 #7 0x08aece19 in llvm::TargetLowering::LowerCallTo (this=0x92b4c58, Chain= {Node = 0x92d1b50, ResNo = 0}, RetTy=0x92aee1...