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...________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > I'm a little confused. If a bundle is supposed to have at least 2 instructions, what is the point of VLIWPacketzierList::isSoloInstruction(...)? Say we have an instruction that can't be bundled with anything, how would one form a packet from it? -- R -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151117/4f7dfdd7/attachment.html>

I'm trying to figure out how Hexagon (I'm using it as an example for my own VLIW) is handling bundles with 1 instruction, but I don't quite get it. Here is the code that I have for a endPacket // endPacket - End the current packet, bundle packet instructions and reset // DFA state. void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,

...ructions. >> - bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB); >> + virtual bool ignorePseudoInstruction(MachineInstr *I, >> + MachineBasicBlock *MBB) { >> + return false; >> + } >> >> - // isSoloInstruction - return true if instruction I must end previous >> - // packet. >> - bool isSoloInstruction(MachineInstr *I); >> + // isSoloInstruction - return true if instruction MI can not be packetized >> + // with any other instruction, which means that MI itself is a packet. &...