Displaying 2 results from an estimated 2 matches for "issideeffects".
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hassideeffects
2016 Aug 22
2
Instruction itineraries and fence/barrier instructions
...a bit too skiddish about this... perhaps the solution
is to change the testcase so that we can ensure that the relative order
between the store and the fence has been preserved.
> Do you mean you want this to avoid scheduling of any instruction around
> any other? Does the instruction have isSideEffects set on it?
Where can I find information about isSideEffects? Googling "LLVm
isSideEffects" didnt' reveal anything that looked relevant.
> I think the fallback if that isn’t enough is to override TargetInstrInfo::
> isSchedulingBoundary
>
>
Thanks, I'll look at that...
2016 Aug 22
3
Instruction itineraries and fence/barrier instructions
We improved our instruction itineraries and now we're seeing our testcases
for fence instructions break.
For example, we have this testcase:
@write_me = external global i32
@read_me = external global i32
; Function Attrs: nounwind
define i32 @xstg_intrinsic(i32 %foo) #0 {
entry:
; CHECK: store r0, r1, 0, 32
; CHECK-NEXT: fence 2
%foo.addr = alloca i32, align 4
store i32 %foo,